Chi Kwong Chang

US Patent:

6346467, Feb 12, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/649027

Inventors:

Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Nagoya, JP
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 213205

US Classification:

438594, 438264, 438595

Abstract:

A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

US Patent:

6356482, Mar 12, 2002

Filed:

Sep 7, 2000

Appl. No.:

09/657029

Inventors:

Narbeh Derhacobian - Belmont CA
Michael Van Buskirk - Saratoga CA
Chi Chang - Redwood City CA
Daniel Sobek - Portola Valley CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 36518503, 36518518

Abstract:

An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.

US Patent:

6381179, Apr 30, 2002

Filed:

Sep 7, 2000

Appl. No.:

09/656675

Inventors:

Narbeh Derhacobian - Belmont CA
Michael Van Buskirk - Saratoga CA
Chi Chang - Redwood City CA
Daniel Sobek - Portola Valley CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 36518528

Abstract:

An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.

US Patent:

6420752, Jul 16, 2002

Filed:

Feb 11, 2000

Appl. No.:

09/502163

Inventors:

Minh Van Ngo - Fremont CA
Yu Sun - Saratoga CA
Fei Wang - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Angela T. Hui - Fremont CA
Mark S. Chang - Los Altos CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257315, 257314, 36518501, 36518526

Abstract:

A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

US Patent:

6429108, Aug 6, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/652136

Inventors:

Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Tokyo, JP
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kawasaki

International Classification:

H01L 213205

US Classification:

438587

Abstract:

A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell with silicon nitride capping and sidewall layers, thereby preventing deleterious oxidation during subsequent processing at high temperature in an oxidizing ambient.

US Patent:

6475847, Nov 5, 2002

Filed:

Mar 27, 2002

Appl. No.:

10/109526

Inventors:

Minh Van Ngo - Fremont CA
Yu Sun - Saratoga CA
Fei Wang - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Angela T. Hui - Fremont CA
Mark S. Chang - Los Altos CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218238

US Classification:

438201, 438211, 438257, 257314, 257315

Abstract:

A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

US Patent:

6549466, Apr 15, 2003

Filed:

Sep 7, 2000

Appl. No.:

09/657143

Inventors:

Narbeh Derhacobian - Belmont CA
Michael Van Buskirk - Saratoga CA
Chi Chang - Redwood City CA
Daniel Sobek - Portola Valley CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 36518526, 36518524

Abstract:

An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.

US Patent:

6754105, Jun 22, 2004

Filed:

May 6, 2003

Appl. No.:

10/430582

Inventors:

Chi Chang - Redwood City CA
Wei Zheng - Santa Clara CA
Hidehiko Shiraiwa - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1604

US Classification:

36518518, 36518528, 257324

Abstract:

A memory device that includes a charge trapping region disposed laterally adjacent a first end of a channel such that energetic electrons traversing the channel can be ballistically injected into the charge trapping region.