Chia Ning Chang

US Patent:

20130179758, Jul 11, 2013

Filed:

Jan 11, 2012

Appl. No.:

13/348447

Inventors:

Guorjuh Thomas Hwang - Sugar Land TX, US
Chia Jen Chang - Sugar Land TX, US

International Classification:

H03M 13/09
G06F 11/10

US Classification:

714801, 714E11032

Abstract:

Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

US Patent:

20210279201, Sep 9, 2021

Filed:

Mar 4, 2020

Appl. No.:

16/809477

Inventors:

- SAN DIEGO CA, US
Chia Heng CHANG - San Diego CA, US

International Classification:

G06F 13/42
H04L 7/00

Abstract:

Clock-data timing in a multi-lane serial data communication link may be adjusted to compensate for drift. A reference lane may be selected and periodically trained to adjust clock-data timing. In response to initiation of a first lane transitioning from an active state to an inactive state, first information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. Then, in response to initiation of the first lane transitioning back from the inactive state to the active state, second information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. The clock-data timing of the first lane may be adjusted based on the first information and the second information.

US Patent:

20180219704, Aug 2, 2018

Filed:

Feb 1, 2017

Appl. No.:

15/422050

Inventors:

- San Diego CA, US
Zhi Zhu - San Diego CA, US
Miao Li - San Marcos CA, US
Li Sun - Irvine CA, US
Deqiang Song - San Diego CA, US
Chia Heng Chang - San Diego CA, US

International Classification:

H04L 25/03
H04L 12/26

Abstract:

Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

US Patent:

20160269034, Sep 15, 2016

Filed:

Mar 13, 2015

Appl. No.:

14/657225

Inventors:

- San Diego CA, US
Behnam Amelifard - San Diego CA, US
Kenneth Luis Arcudia - Cary NC, US
Jon Raymond Boyette - Holly Springs NC, US
Chia Heng Chang - San Diego CA, US
Russell Coleman Deans - Chapel Hill NC, US
Kevin Wayne Spears - Raleigh NC, US

International Classification:

H03L 7/08
G06F 1/12

Abstract:

Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

US Patent:

20140331110, Nov 6, 2014

Filed:

Jul 16, 2014

Appl. No.:

14/333194

Inventors:

- BOISE ID, US
Chia Jen Chang - Sugar Land TX, US

International Classification:

H03M 13/27
G06F 11/10

US Classification:

714801

Abstract:

Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.