Chih Yuan Yang

US Patent:

6440640, Aug 27, 2002

Filed:

Oct 31, 2000

Appl. No.:

09/703092

Inventors:

Chih Yuh Yang - San Jose CA
Christopher F. Lyons - Fremont CA
Harry J. Levinson - Saratoga CA
Khanh B. Nguyen - San Mateo CA
Fei Wang - San Jose CA
Scott A. Bell - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03C 500

US Classification:

430314, 430313, 430316, 430317, 430318

Abstract:

A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

US Patent:

6566230, May 20, 2003

Filed:

Dec 27, 2001

Appl. No.:

10/032630

Inventors:

Harpreet K. Sachar - Sunnyvale CA
Unsoon Kim - Santa Clara CA
Mark S. Chang - Los Altos CA
Chih Y. Yang - San Jose CA
Jayendra D. Bhakta - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03L 2176

US Classification:

438435, 438700

Abstract:

A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.

US Patent:

6544885, Apr 8, 2003

Filed:

Nov 3, 2000

Appl. No.:

09/706498

Inventors:

Khanh B. Nguyen - Sunnyvale CA
Harry J. Levinson - Saratoga CA
Christopher F. Lyons - Fremont CA
Scott A. Bell - San Jose CA
Fei Wang - San Jose CA
Chih Yuh Yang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2358

US Classification:

438631, 438950, 438717

Abstract:

A method of forming a conductor pattern on a base with uneven topography includes placing conductor material on the base, placing a hard mask material on the conductor material, planarizing an exposed surface of the hard mask material, and placing a layer of resist on the hard mask material. The resist is patterned and the patterned resist is used in selectively etching the hard mask material, with the hard mask material used in selectively etching the underlying conductor material. By planarizing the hard mask material prior to placing a layer of resist thereupon, uniformity of the resist coating is enhanced and depth of focus problems in exposing the resist are reduced.

US Patent:

6653735, Nov 25, 2003

Filed:

Jul 30, 2002

Appl. No.:

10/209447

Inventors:

Chih Yuh Yang - San Jose CA
Douglas Bonser - Austin TX
Pei-Yuan Gao - San Jose CA
Lu You - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257758, 257759

Abstract:

A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pattern to be formed in a patternable layer. The patternable layer is formed over a substrate. A multi-layered anti-reflective coating is formed over the patternable layer. A photoresist pattern is formed on the coating. The coating may comprise an amorphous carbon layer formed over the patternable layer and a SiC layer having a lower pinhole density than the pinhole density of SiON formed over the amorphous carbon layer. The coating may also be formed over a polysilicon layer and comprise a thermal expansion buffer layer having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon.

US Patent:

6740566, May 25, 2004

Filed:

Sep 17, 1999

Appl. No.:

09/398641

Inventors:

Christopher F. Lyons - Fremont CA
Scott A. Bell - San Jose CA
Harry J. Levinson - Saratoga CA
Khanh B. Nguyen - Sunnyvale CA
Fei Wang - San Jose CA
Chih Yuh Yang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2176

US Classification:

438424, 438221, 438296

Abstract:

In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench. In another embodiment, the method further involves depositing an insulating filler material into the shallow trench to provide a shallow trench isolation region.

US Patent:

6750127, Jun 15, 2004

Filed:

Feb 14, 2003

Appl. No.:

10/367407

Inventors:

Mark S. Chang - Los Altos CA
Darin Chan - Campbell CA
Chih Yuh Yang - San Jose CA
Lu You - San Jose CA
Scott A. Bell - San Jose CA
Douglas J. Bonser - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438585, 438766, 438778

Abstract:

An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.

US Patent:

6764947, Jul 20, 2004

Filed:

Feb 14, 2003

Appl. No.:

10/366801

Inventors:

Darin Chan - Campbell CA
Douglas J. Bonser - Austin TX
Marina V. Plat - San Jose CA
Marilyn I. Wright - Austin TX
Chih Yuh Yang - San Jose CA
Lu You - San Jose CA
Scott A. Bell - San Jose CA
Philip A. Fisher - Foster City CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438645, 438706, 438639

Abstract:

A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.

US Patent:

6797552, Sep 28, 2004

Filed:

Nov 19, 2002

Appl. No.:

10/299434

Inventors:

Mark S. Chang - Los Altos CA
Douglas J. Bonser - Austin TX
Marina V. Plat - San Jose CA
Chih Yuh Yang - San Jose CA
Scott A. Bell - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438197, 438717, 438719, 438735

Abstract:

A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.