Chih H Yang

US Patent:

6764949, Jul 20, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/334392

Inventors:

Douglas J. Bonser - Austin TX
Marina V. Plat - San Jose CA
Chih Yuh Yang - San Jose CA
Scott A. Bell - San Jose CA
Darin Chan - Campbell CA
Philip A. Fisher - Foster City CA
Christopher F. Lyons - Fremont CA
Mark S. Chang - Los Altos CA
Pei-Yuan Gao - San Jose CA
Marilyn I. Wright - Austin TX
Lu You - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438666, 438703

Abstract:

A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.

US Patent:

6849530, Feb 1, 2005

Filed:

Dec 30, 2002

Appl. No.:

10/334337

Inventors:

Douglas J. Bonser - Austin TX, US
Marina V. Plat - San Jose CA, US
Chih Yuh Yang - San Jose CA, US
Scott A. Bell - San Jose CA, US
Philip A. Fisher - Foster City CA, US
Christopher F. Lyons - Fremont CA, US

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438585, 438595, 438636

Abstract:

To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

US Patent:

7268066, Sep 11, 2007

Filed:

Aug 19, 2004

Appl. No.:

10/922093

Inventors:

Douglas J. Bonser - Austin TX, US
Marina V. Plat - San Jose CA, US
Chih Yuh Yang - San Jose CA, US
Scott A. Bell - San Jose CA, US
Philip A. Fisher - Foster City CA, US
Christopher F. Lyons - Fremont CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/4763

US Classification:

438585, 438595, 438636

Abstract:

To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.