Chin Y Chen

US Patent:

20210057007, Feb 25, 2021

Filed:

Nov 6, 2020

Appl. No.:

17/092046

Inventors:

- Boise ID, US
Luigi Pilolli - L'Aquila, IT
Ali Feiz Zarrin Ghalam - Sunnyvale CA, US
Chin Yu Chen - San Jose CA, US

International Classification:

G11C 7/22
G11C 7/10

Abstract:

Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

US Patent:

20200402554, Dec 24, 2020

Filed:

Jun 20, 2019

Appl. No.:

16/447727

Inventors:

- Boise ID, US
Luigi Pilolli - L'Aquila, IT
Ali Feiz Zarrin Ghalam - Sunnyvale CA, US
Chin Yu Chen - San Jose CA, US

International Classification:

G11C 7/22
G11C 7/10

Abstract:

Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.