Ching K Tai

US Patent:

7271029, Sep 18, 2007

Filed:

Feb 25, 2005

Appl. No.:

11/067113

Inventors:

Ching K. Tai - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

438107, 438113

Abstract:

A package-ready light-sensitive integrated circuit and process for preparing a light-sensitive semiconductor substrate for packaging that provide for a reduced exposure of a light-sensitive integrated circuit to light. The package-ready light-sensitive integrated circuit includes a semiconductor substrate (e. g. , a silicon wafer) with an upper surface and a lower surface and lateral edges, an individual light-sensitive integrated circuit formed in and on the upper surface of the semiconductor substrate, and an opaque material layer covering the lower surface and lateral edges of the semiconductor substrate. The opaque material layer prevents light from entering the semiconductor substrate and interfering with operation of the light-sensitive integrated circuit. The process includes first providing at least one semiconductor substrate with a plurality of light-sensitive integrated circuits formed in and on its upper surface. Next, the semiconductor substrate(s) is diced to form individual light-sensitive integrated circuits, each of which has a semiconductor substrate lower surface and semiconductor substrate lateral edges.

US Patent:

6876052, Apr 5, 2005

Filed:

May 12, 2000

Appl. No.:

09/570181

Inventors:

Ching K. Tai - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L031/0203

US Classification:

257433, 257778, 257787, 257788, 257435, 257436, 438 48, 438 64, 438108

Abstract:

A package-ready light-sensitive integrated circuit and process for preparing a light-sensitive semiconductor substrate for packaging that provide for a reduced exposure of a light-sensitive integrated circuit to light. The package-ready light-sensitive integrated circuit includes a semiconductor substrate (e. g. , a silicon wafer) with an upper surface and a lower surface and lateral edges, an individual light-sensitive integrated circuit formed in and on the upper surface of the semiconductor substrate, and an opaque material layer covering the lower surface and lateral edges of the semiconductor substrate. The opaque material layer prevents light from entering the semiconductor substrate and interfering with operation of the light-sensitive integrated circuit. The process includes first providing at least one semiconductor substrate with a plurality of light-sensitive integrated circuits formed in and on its upper surface. Next, the semiconductor substrate(s) is diced to form individual light-sensitive integrated circuits, each of which has a semiconductor substrate lower surface and semiconductor substrate lateral edges.