Ching L Wang

US Patent:

6621115, Sep 16, 2003

Filed:

Nov 6, 2001

Appl. No.:

10/005495

Inventors:

Ching Dong Wang - Cupertino CA

Assignee:

Integrated Memory Technologies, Inc. - Santa Clara CA

International Classification:

H01L 2976

US Classification:

257314, 438267, 257317

Abstract:

A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

US Patent:

6764905, Jul 20, 2004

Filed:

Jul 9, 2003

Appl. No.:

10/616358

Inventors:

Ching Dong Wang - Cupertino CA

Assignee:

Integrated Memory Technologies, Inc. - Santa Clara CA

International Classification:

H01L 21336

US Classification:

438267, 438266, 438257, 257315

Abstract:

A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

US Patent:

8455537, Jun 4, 2013

Filed:

Jun 21, 2011

Appl. No.:

13/165431

Inventors:

William J. Welsh - Princeton NJ, US
Ching Y. Wang - Cincinnati OH, US
Ni Ai - Piscataway NJ, US

Assignee:

University of Medicine and Dentistry of New Jersey - Somerset NJ

International Classification:

A61K 31/40
A61K 31/12
C07C 253/00
C07D 209/48

US Classification:

514417, 514683, 568329, 548477

Abstract:

A method for preventing, diagnosing, or treating a condition mediated by an estrogen receptor by administering to a patient in need thereof an effective amount of a compound of formula I, II, or a combination thereof: wherein R1, R3, R4, and R5 are independently selected from H, OH, and OR; R2 is selected from H, OH, and (C═O) (C)alkyl; Ris (C)alkyl or (C═O)(C)alkyl; or a derivative of the compound selected from N-oxide derivatives, prodrug derivatives, protected derivatives, isomers, and mixtures of isomers of the compound; or a pharmaceutically acceptable salt or solvate of the compound or the derivative. Compounds of formula I and II and pharmaceuticals compositions thereof are also presented.

US Patent:

46671072, May 19, 1987

Filed:

Jun 19, 1985

Appl. No.:

6/746496

Inventors:

Ching L. Wang - Livermore CA

Assignee:

The United States of America as represented by the United States
Department of Energy - Washington DC

International Classification:

G01T 300

US Classification:

250390

Abstract:

The invention comprises a neutron detector (50) of very high temporal resolution that is particularly well suited for measuring the fusion reaction neutrons produced by laser-driven inertial confinement fusion targets. The detector comprises a biased two-conductor traveling-wave transmission line (54, 56, 58, 68) having a uranium cathode (60) and a phosphor anode (62) as respective parts of the two conductors. A charge line and Auston switch assembly (70, 72, 74) launch an electric field pulse along the transmission line. Neutrons striking the uranium cathode at a location where the field pulse is passing, are enabled to strike the phosphor anode and produce light that is recorded on photographic film (64). The transmission line may be variously configured to achieve specific experimental goals.

US Patent:

44242204, Jan 3, 1984

Filed:

Sep 22, 1982

Appl. No.:

6/421595

Inventors:

Ching C. Wang - San Francisco CA

Assignee:

Merck & Co., Inc. - Rahway NJ

International Classification:

A61K 31495

US Classification:

424250

Abstract:

Fluorouracil and emimycin are useful in the treatment of giardiasis and trichomoniasis.

US Patent:

60750448, Jun 13, 2000

Filed:

Jul 17, 1998

Appl. No.:

9/118451

Inventors:

Ching C. Wang - San Francisco CA
John Somoza - San Francisco CA
Jon P. Page - San Francisco CA
Ronaldus Marcellus Alphonsus Knegtel - Nbijmegen, NL
Irwin D. Kuntz - Greenbrae CA
Connie M. Oshiro - Mountain View CA
A. Geoffrey Skillman - San Francisco CA

Assignee:

The Regents of the University of California - San Francisco CA

International Classification:

A01N 4338

US Classification:

514415

Abstract:

The use of certain heterocyclic derivatives for treating parasitic protozoa infections in mammals, in particular bovine trichomoniasis and giardiasis, is disclosed.

US Patent:

43935125, Jul 12, 1983

Filed:

Jul 7, 1981

Appl. No.:

6/281141

Inventors:

Ching L. Wang - Livermore CA

Assignee:

The United States of America as represented by the United States
Department of Energy - Washington DC

International Classification:

G01N 2322

US Classification:

378156

Abstract:

An apparatus utilizing filter-fluorescer combinations is provided to measure short bursts of high fluence x-rays above 120 keV energy, where there are no practical absorption edges available for conventional filter-fluorescer techniques. The absorption edge of the prefilter is chosen to be less than that of the fluorescer, i. e. , E. sub. PRF E. sub. F. In this way, the response function is virtually zero between E. sub. PRF and E. sub. F and well defined and enhanced in an energy band of less than 1000 keV above the 120 keV energy.

US Patent:

62321854, May 15, 2001

Filed:

May 15, 2000

Appl. No.:

9/570963

Inventors:

Ching D. Wang - Cupertino CA

Assignee:

Integrated Memory Technologies, Inc. - Santa Clara CA

International Classification:

H01L 21336

US Classification:

438266

Abstract:

A method for making a non-volatile memory cell having a select gate, a floating gate and a control gate of the completely self-aligned type, partially self-aligned type and non-aligned type is disclosed. Further, each of the three types of cells has a floating gate, whose linear dimension can be increased beyond the smallest lithographic feature of the process design rule.