Chirag C Patel

US Patent:

6972243, Dec 6, 2005

Filed:

Sep 30, 2003

Appl. No.:

10/674331

Inventors:

Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/301
H01L021/46
H01L021/78

US Classification:

438461, 438460, 438462, 257692

Abstract:

A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a portion of the sacrificial material; and removing portions of the die under the trench so as to separate a portion of the die on one side of the trench from a portion on another side of the trench. The sacrificial material may be patterned so that the channels extend so as to be partially in a portion of the die and partially a portion of the sacrificial material. A series of structures are formed having dies with micro-pins.

US Patent:

7033927, Apr 25, 2006

Filed:

Jun 22, 2004

Appl. No.:

10/872451

Inventors:

Guy M. Cohen - Mohegan Lake NY, US
Daniel C. Edelstein - White Plains NY, US
Keith A. Jenkins - Sleepy Hollow NY, US
Chirag S. Patel - Peekskill NY, US
Lie Shan - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438637, 438411, 438422, 257709

Abstract:

The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the vias may be fully or partially filled with an insulating material having defined conductive properties to further retard heat electromagnetic or heat transmission between the regions. In another embodiment, electrical isolation between two regions is achieved by etching a closed loop or an open loop trench at the border of the regions and filling the trench with a conductive material to provide proper termination of electromagnetic fields within the substrate.

US Patent:

7276787, Oct 2, 2007

Filed:

Dec 5, 2003

Appl. No.:

10/729254

Inventors:

Daniel Charles Edelstein - White Plains NY, US
Paul Stephen Andry - Mohegan Lake NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Jon Alfred Casey - Poughkeepsie NY, US
Sherif A. Goma - Hawthorne NY, US
Raymond R. Horton - Dover Plains NY, US
Gareth Geoffrey Hougham - Ossining NY, US
Michael Wayne Lane - Cortlandt Manor NY, US
Xiao Hu Liu - Croton on Hudson NY, US
Chirag Suryakant Patel - Peekskill NY, US
Edmund Juris Sprogis - Underhill VT, US
Michelle Leigh Steen - Danbury CT, US
Brian Richard Sundlof - Beacon NY, US
Cornelia K. Tsang - Mohegan Lake NY, US
George Frederick Walker - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/498
H01L 21/4763
H01L 29/40
H01L 23/52

US Classification:

257698, 257E23067, 257E23075, 257E23011, 257E25013, 257E21597, 257E23006, 257E23172, 257E23174, 257774, 257773, 257702, 257680, 257700, 257758

Abstract:

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

US Patent:

8143726, Mar 27, 2012

Filed:

Aug 20, 2009

Appl. No.:

12/544894

Inventors:

John U. Knickerbocker - Monroe NY, US
Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257777, 257E25006

Abstract:

A semiconductor device includes a semiconductor chip, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip.

US Patent:

8222079, Jul 17, 2012

Filed:

Sep 28, 2007

Appl. No.:

11/863759

Inventors:

John U. Knickerbocker - Monroe NY, US
Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438108, 257E25006

Abstract:

A semiconductor device includes a carrier, a semiconductor chip formed on the carrier, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip.

US Patent:

8328156, Dec 11, 2012

Filed:

Feb 13, 2012

Appl. No.:

13/371840

Inventors:

Bing Dang - Chappaqua NY, US
Peter A. Gruber - Mohegan Lake NY, US
Luc Guerin - Quebec, CA
Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B28B 7/22
E04G 11/50

US Classification:

249 60, 249117, 257E21586

Abstract:

Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

US Patent:

8405226, Mar 26, 2013

Filed:

Jun 13, 2012

Appl. No.:

13/495195

Inventors:

John U. Knickerbocker - Monroe NY, US
Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257777, 257E25006

Abstract:

A method of fabricating a semiconductor device including forming a micro-chip comprising a thinned-wafer having one or more components fabricated thereon disposed between a carrier and a semiconductor chip, the micro-chip being electrically connected to the semiconductor chip under a higher consumption macro of the semiconductor chip and including a thickness which is less than a thickness of the semiconductor chip, forming an interconnect between the semiconductor chip and the carrier, forming an interconnect between the micro-chip and the semiconductor chip, and forming an interconnect between the micro-chip and the carrier. The micro-chip includes a thinned micro-chip having a thickness of less than 20 microns and the semiconductor chip includes plural semiconductor chips formed as a chip stack. The micro-chip includes a plurality of micro-chips formed on the plural semiconductor chips, such that the semiconductor device is a three-dimensional integrated circuit.

US Patent:

20130181144, Jul 18, 2013

Filed:

Jan 9, 2013

Appl. No.:

13/737594

Inventors:

HONEYWELL INTERNATIONAL INC. - Morristown NJ, US
James Kane - Lawrenceville NJ, US
Carsten Lau - Garbsen, DE
Chirag Patel - Bridgewater NJ, US
Jack Steven Croiter - Brooklyn NY, US

Assignee:

HONEYWELL INTERNATIONAL INC. - Morristown NJ

International Classification:

G01N 21/64
C09K 11/77

US Classification:

2504591, 2504581, 2523014 R, 2502082

Abstract:

Embodiments include methods and apparatus for identifying a thermographic phosphor (e.g., Er:YIG) incorporated on or within an article. The method and apparatus embodiments include an excitation energy generator selectively exposing the article to excitation energy in an absorption band of the thermographic phosphor. An emitted radiation detector detects first emission characteristics of first emitted radiation from the article within an emission band of the thermographic phosphor when the article has a first temperature, and detects second emission characteristics of second emitted radiation from the article within the emission band when the article has a second temperature that is different from the first temperature. A temperature adjustment element is configured to adjust the temperature of the article. Embodiments further include a processing system determining whether the first emission characteristics are sufficiently different from the second emission characteristics.