Chirag B Patel

US Patent:

6972243, Dec 6, 2005

Filed:

Sep 30, 2003

Appl. No.:

10/674331

Inventors:

Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/301
H01L021/46
H01L021/78

US Classification:

438461, 438460, 438462, 257692

Abstract:

A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a portion of the sacrificial material; and removing portions of the die under the trench so as to separate a portion of the die on one side of the trench from a portion on another side of the trench. The sacrificial material may be patterned so that the channels extend so as to be partially in a portion of the die and partially a portion of the sacrificial material. A series of structures are formed having dies with micro-pins.

US Patent:

7033927, Apr 25, 2006

Filed:

Jun 22, 2004

Appl. No.:

10/872451

Inventors:

Guy M. Cohen - Mohegan Lake NY, US
Daniel C. Edelstein - White Plains NY, US
Keith A. Jenkins - Sleepy Hollow NY, US
Chirag S. Patel - Peekskill NY, US
Lie Shan - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438637, 438411, 438422, 257709

Abstract:

The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the vias may be fully or partially filled with an insulating material having defined conductive properties to further retard heat electromagnetic or heat transmission between the regions. In another embodiment, electrical isolation between two regions is achieved by etching a closed loop or an open loop trench at the border of the regions and filling the trench with a conductive material to provide proper termination of electromagnetic fields within the substrate.

US Patent:

7189595, Mar 13, 2007

Filed:

Jun 16, 2004

Appl. No.:

10/771817

Inventors:

John H. Magerlein - Yorktown Heights NY, US
Chirag S. Patel - Peekskill NY, US
Edmund J. Sprogis - Underhill VT, US
Herbert I. Stoller - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/50

US Classification:

438108, 438109, 438459

Abstract:

A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

US Patent:

7230334, Jun 12, 2007

Filed:

Nov 12, 2004

Appl. No.:

10/987985

Inventors:

Paul S. Andry - Yorktown Heights NY, US
Evan G. Colgan - Chestnut Ridge NY, US
Lawrence S. Mok - Brewster NY, US
Chirag S. Patel - Peekskill NY, US
David E. Seeger - Congers NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/46

US Classification:

257713, 257714, 165 804, 165170

Abstract:

Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e. g. , chip packages, system-on-a-package modules, etc. ,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

US Patent:

7276787, Oct 2, 2007

Filed:

Dec 5, 2003

Appl. No.:

10/729254

Inventors:

Daniel Charles Edelstein - White Plains NY, US
Paul Stephen Andry - Mohegan Lake NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Jon Alfred Casey - Poughkeepsie NY, US
Sherif A. Goma - Hawthorne NY, US
Raymond R. Horton - Dover Plains NY, US
Gareth Geoffrey Hougham - Ossining NY, US
Michael Wayne Lane - Cortlandt Manor NY, US
Xiao Hu Liu - Croton on Hudson NY, US
Chirag Suryakant Patel - Peekskill NY, US
Edmund Juris Sprogis - Underhill VT, US
Michelle Leigh Steen - Danbury CT, US
Brian Richard Sundlof - Beacon NY, US
Cornelia K. Tsang - Mohegan Lake NY, US
George Frederick Walker - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/498
H01L 21/4763
H01L 29/40
H01L 23/52

US Classification:

257698, 257E23067, 257E23075, 257E23011, 257E25013, 257E21597, 257E23006, 257E23172, 257E23174, 257774, 257773, 257702, 257680, 257700, 257758

Abstract:

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

US Patent:

7352066, Apr 1, 2008

Filed:

Sep 30, 2003

Appl. No.:

10/675139

Inventors:

Russell A. Budd - North Salem NY, US
Punit P. Chiniwalla - New York NY, US
Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48

US Classification:

257774, 257 13, 257 84, 257432, 257E21597

Abstract:

Method of fabricating a semiconductor die with a microlens associated therewith. More particularly, a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments. Also disclosed are means for transferring, coupling and or focusing light from an electronic-optical device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate. The high alignment accuracies afforded by standard semiconductor fabrication processes are exploited so as to obviate the need for active alignment of the optical coupling or light guiding elements.

US Patent:

7456046, Nov 25, 2008

Filed:

Feb 23, 2005

Appl. No.:

11/063449

Inventors:

Leena Paivikki Buchwalter - Hopewell Junction NY, US
Russell A. Budd - North Salem NY, US
Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438107, 438106, 438584

Abstract:

A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology.

US Patent:

7488680, Feb 10, 2009

Filed:

Aug 30, 2005

Appl. No.:

11/214602

Inventors:

Paul S. Andry - Yorktown Heights NY, US
Chirag S. Patel - Peekskill NY, US
Edmund J. Sprogis - Underhill VT, US
Cornelia K. Tsang - Mohegan Lake NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438624

Abstract:

Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side.