Chirag J Patel

US Patent:

7518225, Apr 14, 2009

Filed:

Oct 4, 2006

Appl. No.:

11/538567

Inventors:

Philip G. Emma - Danbury CT, US
John U. Knickerbocker - Monroe NY, US
Chirag S. Patel - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/02

US Classification:

257686, 257723

Abstract:

A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of the carrier package, and the single-layered chip is communicatively coupled to the multi-layered chip stack through the carrier package so that an electrical signal propagates over a given distance between the single-layered chip and the multi-layered chip stack at substantially a speed of propagation for a single layer chip over the given distance. The single-layered chip can be a processor having multi-cores and the multi-layered chip stack can be a memory cache stack. Interconnect vias, having a density at least as great as 2500 interconnects/cmelectrically couple the single-layered chip and the multi-layered chip stack to the carrier package.

US Patent:

7518229, Apr 14, 2009

Filed:

Aug 3, 2006

Appl. No.:

11/498689

Inventors:

John Michael Cotte - New Fairfield CT, US
Brian Paul Gaucher - New Milford CT, US
Janusz Grzyb - Pfaffikon, CH
Nils Deneke Hoivik - Pleasantville NY, US
Christopher Vincent Jahnes - Upper Saddle River NJ, US
John Ulrich Knickerbocker - Monroe NY, US
Duixian Liu - Scarsdale NY, US
John Harold Magerlein - Yorktown Heights NY, US
Chirag Suryakant Patel - Peekskill NY, US
Ullrich R. Pfeiffer - Yorktown Heights NY, US
Cornelia Kang-I Tsang - Mohegan Lake NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/04

US Classification:

257698, 257685, 257723, 257724, 257728, 257E25005, 257E2501, 257E25011, 257E25012, 257E25029

Abstract:

An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

US Patent:

7526054, Apr 28, 2009

Filed:

Mar 4, 2005

Appl. No.:

11/072562

Inventors:

David Doyle - Quincy MA, US
Hossain Hajimowlana - Merrimack NH, US
Kevin Gagne - Hampstead NH, US
Joseph Bastos - Burlington MA, US
Chirag Patel - Methuen MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04L 7/00

US Classification:

375355, 375376, 375364, 375219, 370505, 370503, 710100, 710306

Abstract:

An apparatus, method, and article to dynamically adjust a data signal using a regenerated clock signal in an emulator to increase communication speed between the emulator and the evaluation board is disclosed. In one embodiment, this is achieved by applying a reference clock signal at a predetermined frequency to a digital circuit. A delayed return data signal is then sampled from the digital circuit. The sampled delayed return data signal is then compared to an expected return data signal. The delayed return data signal is then adjusted as a function of the comparison to increase the communication speed between the emulator and the evaluation board.

US Patent:

7808798, Oct 5, 2010

Filed:

Apr 4, 2008

Appl. No.:

12/062665

Inventors:

John Michael Cotte - New Fairfield CT, US
Brian Paul Gaucher - New Milford CT, US
Janusz Grzyb - Pfaffikon, CH
Nils Deneke Hoivik - Pleasantville NY, US
Christopher Vincent Jahnes - Upper Saddle River NJ, US
John Ulrich Knickerbocker - Monroe NY, US
Duixian Liu - Scarsdale NY, US
John Harold Magerlein - Yorktown Heights NY, US
Chirag Suryakant Patel - Peekskill NY, US
Ullrich R. Pfeiffer - Yorktown Heights NY, US
Cornelia Kang-I Tsang - Mohegan Lake NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 1/18

US Classification:

361763, 361760

Abstract:

An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

US Patent:

20090202028, Aug 13, 2009

Filed:

Apr 22, 2009

Appl. No.:

12/428162

Inventors:

David DOYLE - Quincy MA, US
Hossain HAJIMOWLANA - Merrimack NH, US
Kevin GAGNE - Hampstead NH, US
Joseph BASTOS - Burlington MA, US
Chirag PATEL - Methuen MA, US

Assignee:

ANALOG DEVICES, INC. - Norwood MA

International Classification:

H04L 7/00

US Classification:

375355

Abstract:

An apparatus, method, and article to dynamically adjust a data signal using a regenerated clock signal in an emulator to increase communication speed between the emulator and the evaluation board is disclosed. In one embodiment, this is achieved by applying a reference clock signal at a predetermined frequency to a digital circuit. A delayed return data signal is then sampled from the digital circuit. The sampled delayed return data signal is then compared to an expected return data signal. The delayed return data signal is then adjusted as a function of the comparison to increase the communication speed between the emulator and the evaluation board.

US Patent:

20230009847, Jan 12, 2023

Filed:

May 18, 2022

Appl. No.:

17/747831

Inventors:

- Needham MA, US
Chirag PATEL - Boston MA, US
Crystal REMINGTON - Northborough MA, US
Alan KWOK - Arlington MA, US
Deborah S. JACOBS - Brookline MA, US

International Classification:

G02C 7/04
A61B 3/04

Abstract:

The present disclosure relates to trial scleral lenses, and the resulting scleral lenses, designed for the asymmetric shape of the sclera and/or its chiral properties. In some embodiments, the scleral lenses are also designed for the specific asymmetry associated with different scleral diameters. In addition, as discussed herein, the scleral shape can vary with different conditions of the eye. By designing a set of trial scleral lenses that takes into account these different asymmetric properties of the sclera, a clinician can be more efficient, fitting more eyes with fewer subsequent modifications. The resulting lenses will also achieve a better fit.

US Patent:

20210225513, Jul 22, 2021

Filed:

Jan 22, 2021

Appl. No.:

17/156499

Inventors:

- Cambridge MA, US
Chirag J. PATEL - Boston MA, US

Assignee:

XY.Health Inc. - Cambridge MA

International Classification:

G16H 50/20
G16H 50/70
G16H 10/20
G16H 10/60

Abstract:

The technology disclosed relates to systems and methods for predicting digital twins. The system includes logic to use a machine learning model predict correlation between pairs of persons and save the results in an environmental and phenotypic correlation matrix. The inputs to the machine learning model can include data from individual-level and group-level datasets. The individual-level datasets include administration dataset including clinical data and person dataset including personal data. The group-level datasets include exposome dataset including environmental exposure and subpopulation dataset. The system includes logic to use the environmental and phenotypic correlation matrix as a random effect when determining associations between exposures and outcomes. The system includes a second machine learning model that can take a pair of exposure and outcome and the environmental and phenotypic correlation matrix as input to predict causal association between exposure and outcome.

US Patent:

20200057314, Feb 20, 2020

Filed:

Oct 25, 2019

Appl. No.:

16/664407

Inventors:

- Needham MA, US
Chirag PATEL - Boston MA, US
Crystal REMINGTON - Northborough MA, US
Alan KWOK - Arlington MA, US
Deborah S. JACOBS - Brookline MA, US

International Classification:

G02C 7/04
A61B 3/04

Abstract:

The present disclosure relates to trial scleral lenses, and the resulting scleral lenses, designed for the asymmetric shape of the sclera and/or its chiral properties. In some embodiments, the scleral lenses are also designed for the specific asymmetry associated with different scleral diameters. In addition, as discussed herein, the scleral shape can vary with different conditions of the eye. By designing a set of trial scleral lenses that takes into account these different asymmetric properties of the sclera, a clinician can be more efficient, fitting more eyes with fewer subsequent modifications. The resulting lenses will also achieve a better fit.

Address:

900 S Main St APT 2, Plantsville, CT 06479

VIN:

5FNRL3H60AB109005

Make:

HONDA

Model:

ODYSSEY

Year:

2010