Chong S Lee

US Patent:

6650140, Nov 18, 2003

Filed:

Mar 6, 2002

Appl. No.:

10/093785

Inventors:

Chong H. Lee - San Ramon CA
Reza Asayesh - Menlo Park CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 39, 326 38

Abstract:

A programmable logic device (âPLDâ) includes high speed serial interface (âHSSIâ) circuitry that can support several high speed serial (âHSSâ) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

US Patent:

6653860, Nov 25, 2003

Filed:

Aug 10, 2001

Appl. No.:

09/927793

Inventors:

Om P. Agrawal - Los Altos CA
Xiaojie (Warren) He - Austin TX
Claudia A. Stanley - Austin TX
Larry R. Metzger - Austin TX
Chong M. Lee - Colorado Springs CO

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19177

US Classification:

326 41, 326 38

Abstract:

An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PTs) therefrom. Part or all of the macrocells local 5 PTs may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoPs generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PTs (e. g. , 5 PTs) to having slower generation of sums of a much larger number of PTs (e. g.

US Patent:

6771105, Aug 3, 2004

Filed:

Mar 13, 2002

Appl. No.:

10/099707

Inventors:

Stjepan William Andrasic - Burlingame CA
Rakesh H. Patel - Cupertino CA
Chong H. Lee - San Ramon CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03H 1126

US Classification:

327276, 327266, 327280, 331 57

Abstract:

A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (âVCOâ) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (âPLLâ) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

US Patent:

6842034, Jan 11, 2005

Filed:

Jul 1, 2003

Appl. No.:

10/612253

Inventors:

Vinson Chan - Fremont CA, US
Chong Lee - San Ramon CA, US
Rakesh Patel - Cupertino CA, US
Ramanand Venkata - San Jose CA, US
Binh Ton - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 1900

US Classification:

326 8, 326 37, 326 39

Abstract:

Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.

US Patent:

6848095, Jan 25, 2005

Filed:

May 17, 2002

Appl. No.:

10/150410

Inventors:

Chong M. Lee - Colorado Springs CO, US

Assignee:

Lattice Semiconductor Corp. - Hillsboro OR

International Classification:

G06F 1750
G06F 1900

US Classification:

716 17, 716 16

Abstract:

A method of assigning logic functions to macrocells assures that a maximum number of macrocells are assigned two or more logic functions. A first logic function is assigned to a macrocell without restriction. Rules are then applied to the macrocell to determine whether a second logic function may be assigned to the macrocell, and, if so, whether any restrictions exist on what the second logic function may be.

US Patent:

6888480, May 3, 2005

Filed:

Aug 28, 2003

Appl. No.:

10/652907

Inventors:

Vinson Chan - Fremont CA, US
Chong Lee - San Ramon CA, US
Huy Ngo - Redwood City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03M007/00

US Classification:

341 59, 713500, 360 40

Abstract:

Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. Run-length detection circuitry checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage offered by the circuitry is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i. e. , the clock domain of the detection circuitry and the clock domain of the utilization circuitry).

US Patent:

6911841, Jun 28, 2005

Filed:

Aug 18, 2003

Appl. No.:

10/643276

Inventors:

Chong H. Lee - San Ramon CA, US
Reza Asayesh - Menlo Park CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K019/173

US Classification:

326 38, 326 37

Abstract:

A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

US Patent:

7002368, Feb 21, 2006

Filed:

May 12, 2005

Appl. No.:

11/128916

Inventors:

Chong H. Lee - San Ramon CA, US
Reza Asayesh - Menlo Park CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 41

Abstract:

A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.