Chor Yin Chia

US Patent:

7430140, Sep 30, 2008

Filed:

Sep 23, 2005

Appl. No.:

11/234647

Inventors:

Ritesh Mastipuram - Santa Clara CA, US
Rajesh Manapat - San Jose CA, US
Chor Fung Chia - Fremont CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 7/00

US Classification:

36518917, 365194, 365211, 327176

Abstract:

A memory architecture and a method of operating the same can provide a substantially constant data valid window (DVW) irrespective of a temperature for the memory device. Generally, a memory device can receive an access request, determine a temperature of the memory device, and switch a number of delay elements in an output buffer in response to the temperature of the memory device. In one embodiment, a memory device can have a multi-stage input-output (I/O) buffer and an automatic temperature compensated circuit that samples a temperature of the memory and then switches a number of delay elements in the I/O buffer into a data path between the memory and the output to provide a substantially constant DVW over changes in temperature.

US Patent:

7728807, Jun 1, 2010

Filed:

Feb 1, 2006

Appl. No.:

11/344899

Inventors:

Chor Yin Chia - San Jose CA, US

International Classification:

G09G 3/36

US Classification:

345100

Abstract:

Techniques are provided for producing two output voltages that are substantially symmetric about a middle voltage (VCOM), based on a digital data value stored in a register. A first output voltage is produced based on the digital data value stored in the register. Additionally, the digital data value stored in the register is converted (e. g. , by determining its 2's compliment) to a second digital data value, which is used to produce a second output voltage that is substantially symmetric about VCOM with the first output voltage. Alternatively, the digital data value stored in the register is provided to two different DACs that have their pair of reference voltages swapped (where the reference voltages are symmetric about VCOM), which will result in the outputs of the DACs being substantially symmetric about VCOM.

US Patent:

7907109, Mar 15, 2011

Filed:

Sep 29, 2006

Appl. No.:

11/540698

Inventors:

Chor Yin Chia - San Jose CA, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

G09G 3/36

US Classification:

345 98, 345 95

Abstract:

A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

US Patent:

8384650, Feb 26, 2013

Filed:

Feb 2, 2011

Appl. No.:

13/019558

Inventors:

Chor Yin Chia - San Jose CA, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

G09G 3/36

US Classification:

345100

Abstract:

A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

US Patent:

20060192742, Aug 31, 2006

Filed:

Aug 19, 2005

Appl. No.:

11/207480

Inventors:

Chor Chia - San Jose CA, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

G09G 3/36

US Classification:

345100000

Abstract:

A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

US Patent:

20070146187, Jun 28, 2007

Filed:

Mar 1, 2007

Appl. No.:

11/681127

Inventors:

Chor Chia - San Jose CA, US

Assignee:

INTERSIL AMERICAS INC. - Milpitas CA

International Classification:

H03M 1/66

US Classification:

341144000

Abstract:

A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

US Patent:

20110273430, Nov 10, 2011

Filed:

Feb 4, 2011

Appl. No.:

13/021623

Inventors:

Chor Yin Chia - San Jose CA, US
Hong Joong Kim - San Jose CA, US

Assignee:

INTERSIL AMERICAS INC. - Milpitas CA

International Classification:

G06F 3/038
H03L 5/00

US Classification:

345212, 327333

Abstract:

In an embodiment, a voltage level shifter circuit includes a first terminal configured to be connected to a high voltage supply rail (Vs+), a second terminal configured to be connected to a low voltage supply rail (Vs−), and an output voltage (V) terminal. The voltage level shifter can also include a compensation voltage (V) node. Additionally, the voltage level shifter includes a plurality of switches configurable in a plurality of configurations, and control circuitry configured to control the switches so that in at least one of the configurations a load connected to the output voltage (V) terminal does not draw any power from the low voltage supply rail (Vs−) and the high voltage supply rail (Vs+). The load can be, e.g., a gate drive circuit of a display panel, such as a thin film transistor-liquid crystal display (TFT-LCD) panel, but is not limited thereto.