Chris S Hill

US Patent:

6384466, May 7, 2002

Filed:

Aug 27, 1998

Appl. No.:

09/141070

Inventors:

Chris W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2940

US Classification:

257510, 257760, 257324, 257354, 257513, 257669, 257700, 257691, 257903, 438624, 438641, 438643, 438257, 438435, 438427, 438424, 438668

Abstract:

A multiple dielectric device and its method of manufacture overlaying a semiconductor material, comprising a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

US Patent:

6433378, Aug 13, 2002

Filed:

Feb 11, 2000

Appl. No.:

09/501736

Inventors:

Chris W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27108

US Classification:

257296, 257758, 257759, 257760, 438595, 438624, 438626, 438631, 438637, 438699, 438906, 438 6

Abstract:

A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

US Patent:

6500730, Dec 31, 2002

Filed:

Nov 17, 2000

Appl. No.:

09/715378

Inventors:

Chris W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2176

US Classification:

438439, 438435, 438424, 438592

Abstract:

A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

US Patent:

6596641, Jul 22, 2003

Filed:

Mar 1, 2001

Appl. No.:

09/797898

Inventors:

Mark E. Jost - Boise ID
Chris W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21302

US Classification:

438704, 438935, 438758

Abstract:

A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.

US Patent:

6787877, Sep 7, 2004

Filed:

Dec 27, 2002

Appl. No.:

10/330525

Inventors:

Chris W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2900

US Classification:

257520, 257521, 257523, 257397, 438439, 438435, 438424, 438592, 438430, 438433, 438434, 438710, 438689

Abstract:

A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

US Patent:

6828252, Dec 7, 2004

Filed:

Apr 21, 2004

Appl. No.:

10/830274

Inventors:

Mark E. Jost - Boise ID
Chris W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03L 21302

US Classification:

438738, 438743, 438706

Abstract:

A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.

US Patent:

6905956, Jun 14, 2005

Filed:

Nov 16, 2001

Appl. No.:

09/992462

Inventors:

Chris W. Hill - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L021/4763

US Classification:

438624, 438435, 438763, 438778, 438780, 438784, 438958, 438981

Abstract:

A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

US Patent:

6930058, Aug 16, 2005

Filed:

Apr 21, 2003

Appl. No.:

10/420246

Inventors:

Chris W. Hill - Boise ID, US
Weimin Li - Boise ID, US
Gurtej S. Sandhu - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L021/31
H01L021/469
H01L021/8238
H01L021/76

US Classification:

438783, 438221, 438424, 438433, 438784, 438786

Abstract:

A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two different time periods and under conditions effective to deposit a doped silicon dioxide layer on the substrate. The time periods and conditions are characterized by some period of time when one of said gaseous precursors comprising said dopant is flowed to the chamber in the substantial absence of flowing any of said oxidizer precursor. In one implementation, the time periods and conditions are effective to at least initially deposit a greater quantity of doped silicon dioxide within at least some gaps on the substrate as compared to any doped silicon dioxide deposited atop substrate structure which define said gaps.