Christine M Fuller

US Patent:

56465467, Jul 8, 1997

Filed:

Jun 2, 1995

Appl. No.:

8/460481

Inventors:

Allan Robert Bertolet - Williston VT
Christine Marie Fuller - Williston VT
Scott Whitney Gould - South Burlington VT
Steven Paul Hartman - Jericho VT
Joseph Andrew Iadanza - Hinesburg VT
Frank Ray Keyser - Colchester VT
Eric Ernest Millham - St. George VT
Timothy Shawn Reny - Underhill Center VT
Brian A. Worth - Milton VT
Gulson Yasar - South Burlington VT
Terrance John Zittritsch - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03F 19177

US Classification:

326 39

Abstract:

A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e. g. , clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback.

US Patent:

57649545, Jun 9, 1998

Filed:

Aug 23, 1995

Appl. No.:

8/518515

Inventors:

Christine Marie Fuller - Williston VT
Steven Paul Hartman - Jericho VT
Eric Ernest Millham - St. George VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9455

US Classification:

395500

Abstract:

In a Field Programmable Gate Array ("FPGA") design system, a configuration is generated. A path of the configuration is selected as a critical path for optimization. The critical path is optimized by rerouting connections between the logical primitives of the critical path. Prior to the rerouting, the logical primitives of the critical path may be optimally placed within the FPGA configuration. Optimal performance of the critical path is thus achieved.

US Patent:

57810320, Jul 14, 1998

Filed:

Sep 9, 1996

Appl. No.:

8/707839

Inventors:

Allan Robert Bertolet - Williston VT
Kim P.N. Clinton - Essex Junction VT
Christine Marie Fuller - Williston VT
Scott Whitney Gould - South Burlington VT
Steven Paul Hartman - Jericho VT
Joseph Andrew Iadanza - Hinesburg VT
Frank Ray Keyser - Colchester VT
Eric Ernest Millham - St. George VT
Timothy Shawn Reny - Underhill Center VT
Brian A. Worth - Milton VT
Gulson Yasar - South Burlington VT
Terrance John Zittritsch - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 738
H03K 1921

US Classification:

326 39

Abstract:

A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states. A first logic gate of the plurality of combinational logic circuits has first and second inputs each connected to a respective output node of one of two of the four inverter circuits, and a second logic gate has first and second inputs each connected to a respective output node of one of the other two of the four inverter circuits. The inverter circuits may be implemented as XNOR gates.

US Patent:

57480095, May 5, 1998

Filed:

Sep 9, 1996

Appl. No.:

8/707840

Inventors:

Allan Robert Bertolet - Williston VT
Christine Marie Fuller - Williston VT
Scott Whitney Gould - South Burlington VT
Steven Paul Hartman - Jericho VT
Joseph Andrew Iadanza - Hinesburg VT
Frank Ray Keyser - Colchester VT
Eric Ernest Millham - St. George VT
Timothy Shawn Reny - Underhill Center VT
Brian A. Worth - Milton VT
Gulson Yasar - South Burlington VT
Terrance John Zittritsch - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19177

US Classification:

326 39

Abstract:

A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e. g. , clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback.