Christine A Jones

US Patent:

7685345, Mar 23, 2010

Filed:

Jun 27, 2007

Appl. No.:

11/768934

Inventors:

Deanna Postles Dunn - Poughkeepsie NY, US
Christine Comins Jones - Poughkeepsie NY, US
Arthur J O'Neill - Wappingers Falls NY, US
Vesselina Kirilova Papazova - Highland NY, US
Craig Raymond Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/14
G06F 13/368

US Classification:

710244, 710119, 710120

Abstract:

A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.

US Patent:

8032716, Oct 4, 2011

Filed:

Feb 26, 2008

Appl. No.:

12/037904

Inventors:

Lisa C. Heller - Rhinebeck NY, US
Michael F. Fee - Cold Spring NY, US
Christine C. Jones - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711207, 711E12014, 711E12061

Abstract:

A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.

US Patent:

8250243, Aug 21, 2012

Filed:

Jun 24, 2010

Appl. No.:

12/822704

Inventors:

Deanna Postles Dunn Berger - S Hyde Park NY, US
Ekaterina M. Ambroladze - Wappingers Falls NY, US
Michael Fee - Cold Spring NY, US
Christine C. Jones - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00

US Classification:

710 7, 710 5, 714 1

Abstract:

A computer-implemented method for collecting diagnostic data within a multiprocessor system that includes capturing diagnostic data via a plurality of collection points disposed at a source location within the multiprocessor system, routing the captured diagnostic data to a data collection station at the source location, providing a plurality of buffers within the data collection station, and temporarily storing the captured diagnostic data on at least one of the plurality of buffers, and transferring the captured diagnostic data to a target storage location on a same chip as the source location or another storage location on a same node.

US Patent:

8375155, Feb 12, 2013

Filed:

Jun 23, 2010

Appl. No.:

12/821752

Inventors:

Garrett M. Drapala - Poughkeepsie NY, US
Christine C. Jones - Poughkeepsie NY, US
Pak-Kin Mak - Poughkeepsie NY, US
Craig R. Walters - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/24

US Classification:

710263, 710260, 710264, 370412

Abstract:

Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.

US Patent:

8447930, May 21, 2013

Filed:

Jun 22, 2010

Appl. No.:

12/820528

Inventors:

Deanna P. Berger - Poughkeepsie NY, US
Michael F. Fee - Cold Spring NY, US
Christine C. Jones - Poughkeepsie NY, US
Diana L. Orf - Somerville MA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/14

US Classification:

711130, 711145, 711152

Abstract:

Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.

US Patent:

8447932, May 21, 2013

Filed:

Jun 22, 2010

Appl. No.:

12/820511

Inventors:

Deanna P. Berger - Poughkeepsie NY, US
Michael F. Fee - Cold Spring NY, US
Christine C. Jones - Poughkeepsie NY, US
Diana L. Orf - Somerville MA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/12

US Classification:

711133, 711118

Abstract:

Various embodiments of the present invention merge data in a cache memory. In one embodiment a set of store data is received from a processing core. A store merge command and a merge mask from are also received from the processing core. A portion of the store data to perform a merging operation thereon is identified based on the store merge command. A sub-portion of the portion of the store data to be merged with a corresponding set of data from a cache memory is identified based on the merge mask. The sub-portion is merged with the corresponding set of data from the cache memory.

US Patent:

8521960, Aug 27, 2013

Filed:

Jun 23, 2010

Appl. No.:

12/821736

Inventors:

Deanna P. Berger - Poughkeepsie NY, US
Michael F. Fee - Cold Spring NY, US
Christine C. Jones - Poughkeepsie NY, US
Arthur J. O'Neill - Poughkeepsie NY, US
Diana L. Orf - Somerville MA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711140, 711129, 711169

Abstract:

A method, information processing device, and computer program product mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

US Patent:

20090210629, Aug 20, 2009

Filed:

Feb 15, 2008

Appl. No.:

12/032058

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Christine C. Jones - Poughkeepsie NY, US
Pak-kin Mak - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/08

US Classification:

711135, 711E12022

Abstract:

A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.