Christine D Jones

US Patent:

20130060997, Mar 7, 2013

Filed:

Oct 31, 2012

Appl. No.:

13/664736

Inventors:

International Business Machines Corporation - Armonk NY, US
Michael F. FEE - Cold Spring NY, US
Christine C. JONES - Poughkeepsie NY, US
Arthur J. O'NEILL - Poughkeepsie NY, US
Diana L. ORF - Somerville MA, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/08

US Classification:

711105, 711130, 711E12038

Abstract:

Various embodiments of the present invention mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

US Patent:

20130080705, Mar 28, 2013

Filed:

Nov 20, 2012

Appl. No.:

13/682136

Inventors:

International Business Machines Corporation - Armonk NY, US
Michael F. FEE - Cold Spring NY, US
Christine C. JONES - Poughkeepsie NY, US
Diana L. ORF - Somerville MA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/08

US Classification:

711122

Abstract:

Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.