Christine C Wang

US Patent:

20150178077, Jun 25, 2015

Filed:

Dec 23, 2013

Appl. No.:

14/139263

Inventors:

SRIKANTH T. SRINIVASAN - PORTLAND OR, US
MARK J. DECHENE - HILLSBORO OR, US
YURY N. ILIN - BEAVERTON OR, US
JUSTIN M. DEINLEIN - PORTLAND OR, US
CHRISTINE E. WANG - PORTLAND OR, US
MATTHEW C. MERTEN - HILLSBORO OR, US

International Classification:

G06F 9/30

Abstract:

A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

US Patent:

20150095627, Apr 2, 2015

Filed:

Sep 27, 2013

Appl. No.:

14/040016

Inventors:

Mark J. DECHENE - Hillsboro OR, US
Srikanth T. SRINIVASAN - Portland OR, US
Matthew C. MERTEN - Hillsboro OR, US
Tong LI - Portland OR, US
Christine E. WANG - Portland OR, US

International Classification:

G06F 9/30

US Classification:

712228

Abstract:

In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.

US Patent:

20150006496, Jan 1, 2015

Filed:

Jun 29, 2013

Appl. No.:

13/931860

Inventors:

Ravi RAJWAR - Portland OR, US
Matthew C. MERTEN - Hillsboro OR, US
Christine E. WANG - Portland OR, US
Vijaykumar B. KADGI - Portland OR, US
Rajesh S. PARTHASARATHY - Hillsboro OR, US

International Classification:

G06F 9/46

US Classification:

707703

Abstract:

A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

US Patent:

20150006868, Jan 1, 2015

Filed:

Jun 28, 2013

Appl. No.:

13/930501

Inventors:

Ilya Wagner - Hillsboro OR, US
Matthew C. Merten - Hillsboro OR, US
Frank Binns - Hillsboro OR, US
Christine E. Wang - Portland OR, US
Mayank Bomb - Hillsboro OR, US
Tong Li - Portland OR, US
Thilo Schmitt - Biberach/Riss, DE
MD A. Rahman - Portland OR, US

International Classification:

G06F 9/38

US Classification:

712239

Abstract:

In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

US Patent:

20140201505, Jul 17, 2014

Filed:

Mar 30, 2012

Appl. No.:

13/997837

Inventors:

Matthew C. Merten - Hillsboro OR, US
Tong Li - Portland OR, US
Vijaykumar B. Kadgi - Portland OR, US
Srikanth T. Srinivasan - Portland OR, US
Christine E. Wang - Portland OR, US

International Classification:

G06F 9/30

US Classification:

712226

Abstract:

A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions.