Christopher W Conklin

US Patent:

7461241, Dec 2, 2008

Filed:

Jul 31, 2006

Appl. No.:

11/461153

Inventors:

Christopher R. Conklin - Kingston NY, US
Randall W. Philley - Kingston NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

712220

Abstract:

Reassignment of a physical processor backing a logical processor is performed concurrently to the operation of the processor. The operating state of one physical processor is loaded on another physical processor, such that the logical processor is backed by a different physical processor. This reassignment is performed concurrent to processor operation and transparent to the operating system.

US Patent:

7664940, Feb 16, 2010

Filed:

Nov 7, 2008

Appl. No.:

12/266610

Inventors:

Christopher R. Conklin - Kingston NY, US
Randall W. Philley - Kingston NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

712220

Abstract:

Reassignment of a physical processor backing a logical processor is performed concurrently to the operation of the processor. The operating state of one physical processor is loaded on another physical processor, such that the logical processor is backed by a different physical processor. This reassignment is performed concurrent to processor operation and transparent to the operating system.

US Patent:

8499144, Jul 30, 2013

Filed:

Nov 29, 2010

Appl. No.:

12/955283

Inventors:

Christopher R. Conklin - Stone Ridge NY, US
Michael F. Fee - Cold Spring NY, US
Adolf Martens - Weil im Schoenbuch, DE
Walter Niklaus - Stuttgart, DE
Scott B. Swaney - Germantown NY, US
Tobias Webel - Schwaebisch-Gmuend, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/177

US Classification:

713100

Abstract:

The present invention provides an improved method for updating the settings of a processor or a processor core, respectively, concurrently to the operation of the respective processor system in which the processor or processor core, respectively, is running. This enables the insertion of new scan chain data and thus enabling the modification of the hardware characteristics of the processor.

US Patent:

56110626, Mar 11, 1997

Filed:

Mar 31, 1995

Appl. No.:

8/414961

Inventors:

Charles F. Webb - Poughkeepsie NY
Mark S. Farrell - Pleasant Valley NY
Christopher R. Conklin - Kingston NY
Wen H. Li - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 704

US Classification:

395376

Abstract:

Special millicode instructions accelerate the "inner loop" portion of a millicode routine to execute ESA/390 string instructions. Specifically, these millicode instructions are: Replicate Byte, Find Byte Equal, Find Byte Not Equal, Compare String Bytes instructions.

US Patent:

20150262711, Sep 17, 2015

Filed:

Mar 12, 2014

Appl. No.:

14/205724

Inventors:

- Armonk NY, US
William J. Clarke - Poughkeepsie NY, US
Christopher R. Conklin - Stone Ridge NY, US
William V. Huott - Holmes NY, US
Kevin W. Kark - Poughkeepsie NY, US
Thomas J. Knips - Wappingers Falls NY, US
K. Paul Muller - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/44

Abstract:

Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

US Patent:

20150262713, Sep 17, 2015

Filed:

Sep 30, 2014

Appl. No.:

14/501633

Inventors:

- Armonk NY, US
William J. Clarke - Poughkeepsie NY, US
Christopher R. Conklin - Stone Ridge NY, US
William V. Huott - Holmes NY, US
Kevin W. Kark - Poughkeepsie NY, US
Thomas J. Knips - Wappingers Falls NY, US
K. Paul Muller - Wappingers Falls NY, US

International Classification:

G11C 29/44

Abstract:

Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.