Christopher P Delaney

US Patent:

20220222192, Jul 14, 2022

Filed:

Mar 30, 2022

Appl. No.:

17/709098

Inventors:

- Tokyo, JP
Ali Aiouaz - Irvine CA, US
Christopher Delaney - Irvine CA, US
Leland Thompson - Irvine CA, US

International Classification:

G06F 13/40
G06F 13/42
G06F 9/4401
G06F 8/654

Abstract:

A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence. In one embodiment, the peripheral device is a Non-Volatile Memory Express (NVMe)-compliant data storage device.

US Patent:

20190026244, Jan 24, 2019

Filed:

Sep 27, 2018

Appl. No.:

16/144265

Inventors:

- Tokyo, JP
Ali Aiouaz - Irvine CA, US
Christopher Delaney - Irvine CA, US
Leland Thompson - Irvine CA, US

International Classification:

G06F 13/40
G06F 9/4401
G06F 13/42
G06F 8/654

Abstract:

A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence. In one embodiment, the peripheral device is a Non-Volatile Memory Express (NVMe)-compliant data storage device.

US Patent:

20160268000, Sep 15, 2016

Filed:

Mar 9, 2015

Appl. No.:

14/642609

Inventors:

- San Jose CA, US
Christopher S. DELANEY - Orange CA, US
Gordon W. WAIDHOFER - Irvine CA, US
Ali AIOUAZ - San Jose CA, US

International Classification:

G11C 16/30
G11C 16/16
G11C 11/56

Abstract:

A solid state drive has a power failure savings mode that permits a reduction in holdup time for a temporary backup power supply. The solid state drive stores data in a multi-level cell (MLC) mode. In a power fail saving mode system metadata is written in a pseudo Single Level Cell (pSLC) mode. In the normal operating mode page writes are performed in complete blocks. In the power fail save saving mode data from a write buffer is written and additional dummy pages written to reduce the total number of pages that must be written to below a complete block size with the dummy pages providing protection from data corruption.

US Patent:

20160172014, Jun 16, 2016

Filed:

Dec 15, 2014

Appl. No.:

14/571070

Inventors:

- San Jose CA, US
Christopher DELANEY - Orange CA, US
Leland THOMPSON - TUSTIN CA, US

International Classification:

G11C 7/10
G11C 11/406

Abstract:

On-chip instruction RAM is leveraged as an extension of on-chip data RAM during normal use of a modified Harvard Architecture processor. Unused space in an instruction RAM is detected in a modified Harvard Architecture processor. During operation of the processor this unused space is used to load and store data normally loaded and stored in an on-chip data RAM. A performance penalty associated with swapping out to external memory is reduced. The type of data stored in the unused portion of the instruction RAM may be selected to optimize performance. In one implementation, the unused space in the instruction RAM is used to load and store only a single type of data, such as heap, stack, initialized or uninitialized data.