Christopher Jon Durham

US Patent:

6406980, Jun 18, 2002

Filed:

Aug 24, 2000

Appl. No.:

09/645155

Inventors:

Matthew J. Amatangelo - Austin TX
Christopher McCall Durham - Round Rock TX
Peter Juergen Klim - Austin TX
Stephen Larry Runyon - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21301

US Classification:

438462, 438401, 438800, 438 17, 438 10

Abstract:

A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.

US Patent:

6502220, Dec 31, 2002

Filed:

Mar 15, 1999

Appl. No.:

09/270182

Inventors:

Christopher McCall Durham - Austin TX
Peter Juergen Klim - Austin TX

Assignee:

International Businesss Machines Corporation - Armonk NY

International Classification:

H04L 108

US Classification:

714823, 326121, 326129

Abstract:

A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a complement signal utilized to generate a complement output signal from the complementary logic circuit. Logic means coupled to the output of the complementary logic circuit detect an occurrence of a non-complementary output from the complementary logic circuit. Multiplexing means within the true tree is utilized to selectively replace the true signal with the complement signal within the true tree in response to detection by the logic means of a non-complementary output, such that a non-complementary output is seamlessly detected and rectified.

US Patent:

6507929, Jan 14, 2003

Filed:

Mar 15, 1999

Appl. No.:

09/270468

Inventors:

Christopher McCall Durham - Austin TX
Peter Juergen Klim - Austin TX
Ronald Gene Walther - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 108

US Classification:

714823, 326121, 326129

Abstract:

A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree. A complementary logic circuit has a true tree for producing a true signal and a complement tree for producing a complement signal. The true signal is utilized to generate a true output signal from the complementary logic circuit and the complement signal is utilized to generate a complement output signal from the complementary logic circuit. Multiplexing means within the true and complement trees are utilized to selectively replace the true (complement) signal with the complement (true) signal within the true (complement) tree, such that the complement (true) tree is utilized to correct the occurrence of a proscribed non-complementary condition at the output of the complementary logic circuit to diagnose a defect during diagnostic testing or to override a defect during normal runtime operation.

US Patent:

6522170, Feb 18, 2003

Filed:

Apr 27, 1998

Appl. No.:

09/067153

Inventors:

Christopher McCall Durham - Austin TX
Peter Juergen Klim - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1900

US Classification:

326 93, 326 96

Abstract:

A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.

US Patent:

6532574, Mar 11, 2003

Filed:

Aug 17, 2000

Appl. No.:

09/640537

Inventors:

Christopher McCall Durham - Round Rock TX
Sharad Mehrotra - Austin TX
Alexander Koos Spencer - Austin TX
Barry Duane Williamson - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 6, 716 5

Abstract:

Adjacent signal lines within the critical path of logic within an integrated circuit are checked for capacitive coupling induced signal delay variations resulting from concurrent signal transitions. When found, signal transition overlap is eliminated by delaying the clock edge (rising or falling) triggering the signal driving logic, without necessarily delaying the other clock edge. A delay circuit is incorporated into clock stages for the signal driving logic, and may be selectively actuated to delay the clock edge to particular signal driving logic circuits. Selection of signal lines in which signal transitions are to be delayed may be performed after manufacture of the integrated circuit, and iterative determinations may be required since signal adjustment may create new critical paths within the integrated circuit logic. Once the final signal adjustment configuration is determined, that configuration may be stored as a vector within a memory in the integrated circuit and read during power-up into a scan chain controlling the individual delay circuits.

US Patent:

6577152, Jun 10, 2003

Filed:

May 28, 1999

Appl. No.:

09/322040

Inventors:

Christopher McCall Durham - Round Rock TX
Peter Juergen Klim - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1716

US Classification:

326 21, 326 23, 326 24

Abstract:

A noise suppression circuit for suppressing above-ground noise is disclosed. The noise suppression circuit for suppressing noises includes a first inverter, a second inverter, and a one-shot circuit. The first inverter, connected to an input line, switches at a first voltage value above which a noise-coupling event is suspected. The second inverter, also connected to the input line, switches at a second voltage value above which a full-switch input is assumed. A first transistor is coupled to the input line. A second transistor passes an output of the second inverter to a gate of the first transistor when an output of the one-shot circuit is high. The third transistor holds the gate of the first transistor low when the output of the one-shot circuit is low.

US Patent:

6650592, Nov 18, 2003

Filed:

Nov 29, 2001

Appl. No.:

09/998044

Inventors:

Matthew J. Amatangelo - Austin TX
Christopher M. Durham - Round Rock TX
Peter Juergen Klim - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 800

US Classification:

365233, 365203

Abstract:

A system, method, and computer program product are disclosed for automatically performing timing checks on a memory cell. A static timing tool is provided that includes multiple, different standard timing elements. Each standard timing element is associated with one or more standard timing checks. The memory cell is represented using one or more of the standard timing elements. Standard timing checks associated with the timing elements used to represent the memory cell are used to verify timing in the memory cell.

US Patent:

6654937, Nov 25, 2003

Filed:

Aug 10, 2000

Appl. No.:

09/637324

Inventors:

Matthew J. Amatangelo - Austin TX
Christopher McCall Durham - Round Rock TX
Peter Juergen Klim - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 6

Abstract:

A method and apparatus is provided for enabling a static timing tool to analyze and test register files in integrated circuits to find correct paths and ignore detected contention. This is achieved by utilizing pattern matching in the static timing tool and having the tool perform certain operations on the transistors of the pattern matched. The methodology includes considering the write word lines as clock nodes, disabling signal propagation through the memory element components, forcing predetermined internal nodes to be of inverse polarity, establishing signal direction through the circuit elements, and indicating that one or more of the predetermined nodes are not to be reported.