Christopher L Durham

US Patent:

55924263, Jan 7, 1997

Filed:

Apr 27, 1995

Appl. No.:

8/429441

Inventors:

Derwin L. Jallice - Reston VA
Christopher M. Durham - Austin TX
Michael K. Ciraula - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 700

US Classification:

365203

Abstract:

An extended segmented precharge architecture for static random access memories includes a logic circuitry on an SRAM chip to keep track as to whether a given bit line has been read out. As long as a given bit line has not been read out, precharge of the equalization lines is eliminated thereby increasing access cycle time and reducing power dissipation. The architecture can be applied to any size SRAM of any organization.

US Patent:

53011651, Apr 5, 1994

Filed:

Oct 28, 1992

Appl. No.:

7/967366

Inventors:

Michael K. Ciraula - Manassas VA
Christopher M. Durham - Austin TX
Derwin L. Jallice - Reston VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 700

US Classification:

3652335

Abstract:

A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to select mode, there appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such a false transition as an actual transition, local clock pulse generators are used which only detect high to low transitions in the chip select mode.

US Patent:

49691252, Nov 6, 1990

Filed:

Jun 23, 1989

Appl. No.:

7/370941

Inventors:

Michael K.. Ciraula - Manassas VA
Christopher Mc. Durham - Manassas VA
Reginald E. Harrison - Falls Church VA
Derwin J. Jallice - Reston VA
Dave C. Lawson - Manassas, all of' VA
Craig L. Stephen - Manassas, all of' VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1140

US Classification:

365203

Abstract:

An improved memory array having row address inputs connected to a row address decoder and column address inputs connected to a column address decoder, the row address decoder and column address decoder having an address bus connected thereto, the memory being organized into an array of word lines organized into rows and columns having a pair of bit lines for each column, the improvement comprising, segmenting the array into a plurality of segments, each segment containing a portion of all of the bit lines; a bit equalization circuit for each segment, to equalize the potential on each bit line in the bit line pair when activated; an equalization circuit control means, having an input coupled to the input address lines, and an output connected to each equalization circuit on each respective segment of the array, for enabling the equalization circuits on those segments of the array which are not selected by the input address and for disabling the equalization circuits on that segment of the array which is selected by the input address; the bit line pairs in the non-selected circuits being maintained in an equal potential state so that when one of the bit lines in a bit line pair in a non-selected segment suffers a discharge due to an ionizing radiation effect, the activated equalization circuit on the non-selected segment will equalize the potential thereof; whereby the radiation immunity of the memory array is improved. The resulting memory array has enhanced radiation hardness, reduced power dissipation, and is capable of static page mode operation.

US Patent:

49966707, Feb 26, 1991

Filed:

Sep 28, 1989

Appl. No.:

7/414889

Inventors:

Michael K. Ciraula - Manassas VA
Christopher M. Durham - Manassas VA
Derwin L. Jallice - Reston VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 700
G11C 1140
G11C 11407

US Classification:

365200

Abstract:

A fused, redundancy selection circuit is disclosed which is disabled by the absence of a chip select signal. The circuit has the feature of avoiding the use of nodes with a floating potential and in this manner it provides an enhanced radiation hardened characteristic. The circuit is effectively disabled if no redundancy is required on a particular memory chip, by leaving fuses which are a part of the circuit, intact. Alternately, if the memory chip is tested to have defects, the redundancy circuit is selectively enabled to provide the desired redundancy for the chip, by blowing fuses which are a part of the circuit. Thereafter, the redundancy circuit is now an active part of the memory chip and it is selectively enabled when the chip select signal is applied to the chip. An advantageous feature of the circuit is that it does not dissipate power when its function is not required either because its enabling fuses have not been blown or alternately when the chip select signal is off. In this manner, a zero standby power, radiation hardened memory redundancy circuit has been provided.

US Patent:

51461110, Sep 8, 1992

Filed:

Apr 10, 1991

Appl. No.:

7/683236

Inventors:

Michael K. Ciraula - Manassas VA
Christopher M. Durham - Manassas VA
Derwin L. Jallice - Reston VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 513

US Classification:

3072963

Abstract:

A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.