Christopher A Graves

US Patent:

6414533, Jul 2, 2002

Filed:

Nov 23, 1999

Appl. No.:

09/447929

Inventors:

Christopher Michael Graves - Sherman TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 508

US Classification:

327319, 327318, 327321

Abstract:

A CMOS bus switch ( ) having undershoot protection circuitry ( ) to help prevent data corruption when the switch is open and the buses (A,B) are isolated from one another. A bias generator ( ) sets a voltage (Bias) referenced to ground which allows the active pull-up clamp to turn on when the bus voltage goes negative. This clamp attempts to counteract the undershoot voltage and limit the Vgd or Vgs of the N-channel pass transistor (MN ) and the Vbe of the parasitic NPN transistor. Since the active pull-up clamp circuit is also over-voltage tolerant, this invention will work equally well in high, low, and mixed voltage systems.

US Patent:

6847235, Jan 25, 2005

Filed:

Dec 18, 2002

Appl. No.:

10/322894

Inventors:

Christopher M. Graves - Sherman TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 508

US Classification:

327106, 327112, 327546, 327309, 326 30

Abstract:

An output driver includes a predriver circuit coupled to a complimentary MOS transistor pair. Third and fourth complimentary MOS transistors are coupled between a source-drain pair of the first and second MOS transistors, respectively and an output. The back gate of at least one of the third and fourth transistors is coupled to the output to provide a lower Vat the beginning of a transition without creating excessive undershoot or overshoot. A diode is coupled in parallel with the source-drain paths of the third and fourth transistors.

US Patent:

7030659, Apr 18, 2006

Filed:

Aug 24, 2004

Appl. No.:

10/926171

Inventors:

Christopher M. Graves - Sherman TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19/20
H03K 19/173
H03K 17/04
H03K 17/16
G06F 7/38

US Classification:

326113, 326 26, 326 27, 326 37, 326 38, 327374

Abstract:

An electronic switch applies ground potential to the backgate of a MOS pass transistor when the transistor is in the off state and the switch is open, during normal conditions. When the transistor is switched to the on state and the switch is closed, the gate voltage is applied to the backgate of the pass transistor in order to reduce the threshold voltage and the on resistance. During an undershoot condition, the gate of the pass transistor is connected to the negative voltage applied to an input port and this voltage is also connected to the backgate of the pass transistor to prevent the pass transistor from being biased on or the parasitic NPN transistor from being biased on and transmitting the input glitch to the output.

US Patent:

8009395, Aug 30, 2011

Filed:

Nov 7, 2007

Appl. No.:

11/936568

Inventors:

Christopher Michael Graves - Sherman TX, US
John Edward Esquivel - Sherman TX, US
James Craig Spurlin - Sherman TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 3/20

US Classification:

361 56, 361 911, 361111

Abstract:

Methods and apparatus for over-voltage protection of device inputs are disclosed. An example apparatus to protect a device from an over-voltage condition disclosed herein comprises a switch coupled between a device input and at least one component of the device, and a voltage compensator to pull a control input of the switch to a voltage associated with the device input to open the switch to protect the device component from the over-voltage condition.

US Patent:

6268759, Jul 31, 2001

Filed:

Nov 23, 1999

Appl. No.:

9/447928

Inventors:

Christopher Michael Graves - Sherman TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 17687

US Classification:

327437

Abstract:

A low voltage CMOS bus switch (20) adapted to connect to a 5V bus (A,B) in a controlled and power-efficient manner. A voltage reference circuit (30) monitors the state of the power supply (Vcc) and provides three control signals (Dref, Dref2, Dref3) when the supply (V. sub. cc) is powered up or down. These control signals help to keep the switch open when the supply is powered down, and are used in the 5V tolerant circuitry to bias the gates of the pass transistors (MN1,MP1) when the supply is powered up. When the bus voltages are below Vcc, the device operates as a normal low voltage bus switch. As the input voltage increases above Vcc, a P-channel pass transistor (MR1) turns off and a gate voltage of a N-channel pass transistor (MN1) is controlled by the tolerant circuitry. This provides a reliable output signal to either a 3. 3V or 5V bus.

US Patent:

61007196, Aug 8, 2000

Filed:

Dec 28, 1998

Appl. No.:

9/221886

Inventors:

Christopher M. Graves - Sherman TX
Steven E. Marum - Sherman TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 190175

US Classification:

326 86

Abstract:

A control circuit for a low-voltage bus switch where the control circuit keeps the bus switch open by stealing power from switch I/O terminals during the loss of supply voltage and thereby maintaining bus isolation. The control circuit also provides a good high level and presents a low switch impedance.

US Patent:

20200226540, Jul 16, 2020

Filed:

Jan 8, 2020

Appl. No.:

16/737726

Inventors:

- Dallas TX, US
Christopher Carter Graves - Dallas TX, US

Assignee:

Omnicounts, LLC - Dallas TX

International Classification:

G06Q 10/08
H04L 9/06

Abstract:

A cryptographically enforced ordering and hierarchical ledger for the distributed collection and processing of inventory data across multiple locations, areas and items is provided.

US Patent:

20190007046, Jan 3, 2019

Filed:

Jun 28, 2017

Appl. No.:

15/635924

Inventors:

- Dallas TX, US
Christopher Michael Graves - Sherman TX, US

International Classification:

H03K 19/0185
H03K 19/00
H03K 17/16

Abstract:

A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.