Christopher S Greer

US Patent:

7114054, Sep 26, 2006

Filed:

May 9, 2003

Appl. No.:

10/434655

Inventors:

Christopher Alan Greer - Allen TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/10

US Classification:

711207, 711173, 711128

Abstract:

Systems and methods for increasing transaction entries in a hardware queue of the type having a fixed number of storage elements. One of a plurality of transaction entries in one of the storage elements is accessed through at least one pointer having one or more first bits that identify the one element and one or more second bits that identify the one transaction entry within the one element. Information that is part of the one transaction entry is modified when the one transaction entry is accessed from the one storage element.

US Patent:

7216205, May 8, 2007

Filed:

Jan 12, 2004

Appl. No.:

10/756436

Inventors:

Christopher Alan Greer - Allen TX, US
Michael Alex Schroeder - Dallas TX, US
Gary Belgrave Gostin - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711147, 711169, 707200, 707201, 709205, 709212, 709213, 709230, 709232, 712225

Abstract:

Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.

US Patent:

7774562, Aug 10, 2010

Filed:

Sep 17, 2004

Appl. No.:

10/944524

Inventors:

Richard W. Adkisson - Dallas TX, US
Christopher Greer - Allen TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/36

US Classification:

711156, 711144, 711148, 711153

Abstract:

A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.

US Patent:

20040225820, Nov 11, 2004

Filed:

May 9, 2003

Appl. No.:

10/434657

Inventors:

Richard Adkisson - Dallas TX, US
Christopher Greer - Allen TX, US

International Classification:

G06F013/36

US Classification:

710/306000

Abstract:

Systems and methods generate transaction identifiers. A plurality of available transaction identifiers are generated for use in identifying future transactions from a first bus. A new transaction identifier is generated upon receipt of each received transaction from the first bus. One of the available transaction identifiers is assigned to each received transaction prior to generation of the new transaction identifier so that the received transaction communicated on a second bus is identified by the one transaction identifier.

US Patent:

20060023819, Feb 2, 2006

Filed:

Jul 29, 2004

Appl. No.:

10/901762

Inventors:

Richard Adkisson - Dallas TX, US
Gary Gostin - Plano TX, US
Christopher Greer - Allen TX, US

International Classification:

H04L 7/00

US Classification:

375354000

Abstract:

A clock synchronizer for effectuating data transfer between first and second clock domains by utilizing first and second synchronizer controllers. The first synchronizer controller circuit operates in the first clock domain which has N first clock cycles and the second synchronizer controller circuit operates in the second clock domain which has M second clock cycles, wherein N/M≧1. Inversion circuitry inverts a first clock signal associated with the first clock domain to generate an inverted first clock signal which is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain.

US Patent:

20080270708, Oct 30, 2008

Filed:

Apr 30, 2007

Appl. No.:

11/741858

Inventors:

Craig Warner - Richardson TX, US
Bryan Hornung - Richardson TX, US
Chris Michael Brueggen - Richardson TX, US
Ryan L. Akkerman - Richardson TX, US
Michael K. Dugan - Richardson TX, US
Gary Gostin - Richardson TX, US
Harvey Ray - Ft. Collins CO, US
Dan Robinson - Richardson TX, US
Christopher Greer - Richardson TX, US

International Classification:

G06F 12/08

US Classification:

711146, 711E12041

Abstract:

A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches.