Christopher A Hess

US Patent:

6475871, Nov 5, 2002

Filed:

Nov 17, 2000

Appl. No.:

09/715851

Inventors:

Brian E. Stine - Santa Clara CA
Christopher Hess - San Ramon CA
Larg H. Weiland - San Ramon CA

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

H02L 2120

US Classification:

438381, 324754

Abstract:

A test structure for analyzing failures due to fabrication induced defects in integrated circuits includes a matrix of bit cells formed by word lines and bit lines. An associated word line probe pad is electrically connected to each word line and an associated bit line probe pad electrically connected to each bit line. A test structure is electrically connected between a word line and a bit line of an associated bit cell. Each test structure has at least one variable attribute which is used to detect defects and create yield models.

US Patent:

6787800, Sep 7, 2004

Filed:

Jul 24, 2002

Appl. No.:

10/202278

Inventors:

Larg H. Weiland - San Ramon CA
Christopher Hess - San Ramon CA

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

H01L 2910

US Classification:

257 48, 257774

Abstract:

A test vehicle has a plurality of the zig-zag structures which include: a first layer having a plurality of first elongated patterns oriented in a first direction; a second layer having a plurality of second elongated patterns oriented in a second direction substantially perpendicular to the first direction; and a plurality of vias or contacts conductively coupling ones of the first patterns to respective ones of the second patterns.

US Patent:

6834375, Dec 21, 2004

Filed:

Sep 16, 2002

Appl. No.:

10/130380

Inventors:

Brian E. Stine - Los Altos Hills CA
Christopher Hess - San Ramon CA
Larg H. Weiland - San Ramon CA
Dennis J. Ciplickas - San Jose CA
John Kibarian - Los Altos Hills CA

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 2, 716 4

Abstract:

A characterization vehicle includes at least one combinatorial logic circuit element, and a control circuit that controls the combinatorial logic circuit element. The control circuit includes an input mechanism for inputting a test pattern of signals into the combinatorial logic circuit element. An output mechanism stores an output pattern that is output by the combinatorial logic circuit element based on the test pattern. A ring bus connects the output means to the input means so as to cause oscillation. A counter counts a frequency of the oscillation, thereby to measure performance of the combinatorial logic circuit element.

US Patent:

6901564, May 31, 2005

Filed:

Jul 18, 2002

Appl. No.:

10/200045

Inventors:

Brian E. Stine - Los Altos Hills CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F017/50
G06F019/00

US Classification:

716 4, 700121

Abstract:

A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.

US Patent:

7024642, Apr 4, 2006

Filed:

Mar 12, 2002

Appl. No.:

10/471775

Inventors:

Christopher Hess - San Ramon CA, US
David Stashower - Los Gatos CA, US
Brian E. Stine - Santa Clara CA, US
Larg H. Weiland - San Ramon CA, US
Richard Burch - McKinney TX, US
Dennis J. Ciplickas - San Jose CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/45
H01L 23/58

US Classification:

716 4, 257 48, 716 5, 716 19

Abstract:

A characterization vehicle includes a substrate having at least one layer (), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (), each pair of nested serpentine lines having a shared pad between them ().

US Patent:

7154115, Dec 26, 2006

Filed:

Mar 26, 2003

Appl. No.:

10/508506

Inventors:

Brian E. Stine - Santa Clara CA, US
Christopher Hess - San Ramon CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

H01L 23/58
H01L 29/10

US Classification:

257 48, 438 18

Abstract:

A test vehicle () comprises a substrate (), a plurality of nested serpentine lines () on the substrate, and a plurality of test pads () on the substrate. Each serpentine line has a plurality of turn sections that comprise two parallel line segments connected by a perpendicular line segment. Each of the plurality of test pads is connected to a respective turn section of a respective one of the nested serpentine lines. Each pair of test pads connected to one of the subset of the nested serpentine lines has at least a respectively different turn section portion connected therebetween.

US Patent:

7174521, Feb 6, 2007

Filed:

Mar 10, 2005

Appl. No.:

11/078630

Inventors:

Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 703 2

Abstract:

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

US Patent:

7197726, Mar 27, 2007

Filed:

Sep 27, 2002

Appl. No.:

10/490908

Inventors:

Dennis J. Ciplickas - San Jose CA, US
Markus Decker - Munich, DE
Christopher Hess - San Ramon CA, US
Brian E. Stine - Santa Clara CA, US
Larg H. Weiland - San Ramon CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 17/50
H01L 25/48
G01R 31/26

US Classification:

716 4, 438 11, 257 48

Abstract:

A test structure combines a first structure () for erosion evaluation with a second structure () for extraction of defect size distributions. The first structure () is a loop structure usable determine a resistance value that varies with metal height. The second structure is a NEST structure (). Loop lines of the loop structure () are connected on both sides of the NEST structure ().