Christopher S Hill

US Patent:

6368986, Apr 9, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/652188

Inventors:

William Budge - Homedale ID
Gurtej S. Sandhu - Boise ID
Christopher W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2106

US Classification:

438787, 438165, 438530, 438766, 438911

Abstract:

A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

US Patent:

6372643, Apr 16, 2002

Filed:

Apr 7, 1998

Appl. No.:

09/056309

Inventors:

Christopher W. Hill - Boise ID
Weimin Li - Boise ID
Gurtej S. Sandhu - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2144

US Classification:

438674, 438681, 438683, 438685, 438643

Abstract:

A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of a semiconductor device structure may be treated in a plasma to enhance the adhesiveness of a selective contact thereto. The semiconductor device structure is positioned within a reaction chamber, wherein a selective contact is deposited onto the exposed semiconductor substrate regions, Any residual selective contact material may be removed from oxide surfaces either intermediately or after selective contact deposition. While the semiconductor device remains in the reaction chamber, a local interconnect is deposited over the semiconductor device structure. The local interconnect may then be patterned. Subsequent layers may be deposited over the local interconnect.

US Patent:

6503851, Jan 7, 2003

Filed:

Aug 3, 2001

Appl. No.:

09/921539

Inventors:

William Budge - Homedale ID
Gurtej S. Sandhu - Boise ID
Christopher W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2131

US Classification:

438787

Abstract:

A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.

US Patent:

6602807, Aug 5, 2003

Filed:

Nov 18, 2002

Appl. No.:

10/298867

Inventors:

William Budge - Homedale ID
Gurtej S. Sandhu - Boise ID
Christopher W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2131

US Classification:

438787

Abstract:

A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.

US Patent:

6617230, Sep 9, 2003

Filed:

Sep 18, 2001

Appl. No.:

09/955503

Inventors:

William Budge - Homedale ID
Gurtej S. Sandhu - Boise ID
Christopher W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 214763

US Classification:

438595, 438778, 438787, 438788

Abstract:

A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is described. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Compared to the deposition rate on exposed regions on non-doped silicon, the silicon oxide deposits at a faster rate on exposed regions of P-type silicon and at a slower rate on exposed regions of N-type silicon.

US Patent:

6777351, Aug 17, 2004

Filed:

Apr 3, 2003

Appl. No.:

10/407625

Inventors:

Christopher W Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2131

US Classification:

438783, 438794, 438799

Abstract:

A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely-spaced regions and a second thickness over the widely-spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely-spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely-spaced regions.

US Patent:

6808983, Oct 26, 2004

Filed:

Aug 27, 2002

Appl. No.:

10/229445

Inventors:

Christopher W. Hill - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438255, 438396, 438964

Abstract:

A storage capacitor plate for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to formed a substantially continuous porous conductive layer.

US Patent:

6924969, Aug 2, 2005

Filed:

May 19, 2004

Appl. No.:

10/849741

Inventors:

Christopher W. Hill - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01G004/005

US Classification:

361303, 361305, 3613063, 257 68, 438253

Abstract:

A storage capacitor plate for a semiconductor assembly having a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to form a substantially continuous porous conductive layer.