Christopher J Mayer

US Patent:

7498960, Mar 3, 2009

Filed:

Apr 19, 2007

Appl. No.:

11/788094

Inventors:

James Wilson - Foxboro MA, US
Joshua A. Kablotsky - Carlisle MA, US
Yosef Stein - Sharon MA, US
Christopher M. Mayer - Dover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 7/00

US Classification:

341106, 341 50

Abstract:

A compute system for executing an h. 264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.

US Patent:

7877430, Jan 25, 2011

Filed:

Mar 26, 2007

Appl. No.:

11/728427

Inventors:

James Wilson - Foxboro MA, US
Joshua Kablotsky - Carlisle MA, US
Yosef Stein - Sharon MA, US
Colm J. Prendergast - Cambridge MA, US
Gregory M. Yukna - Norton MA, US
Christopher M. Mayer - Dover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 17/10

US Classification:

708319

Abstract:

Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

US Patent:

8024551, Sep 20, 2011

Filed:

Oct 26, 2005

Appl. No.:

11/258801

Inventors:

James Wilson - Foxboro MA, US
Joshua A. Kablotsky - Carlisle MA, US
Yosef Stein - Sharon MA, US
Colm J. Prendergast - Cambridge MA, US
Gregory M. Yukna - Norton MA, US
Christopher M. Mayer - Dover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 9/00

US Classification:

712220

Abstract:

Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

US Patent:

8285972, Oct 9, 2012

Filed:

Oct 26, 2005

Appl. No.:

11/258662

Inventors:

James Wilson - Foxboro MA, US
Joshua A. Kablotsky - Carlisle MA, US
Yosef Stein - Sharon MA, US
Christopher M. Mayer - Dover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 9/34

US Classification:

711220, 711206, 345602

Abstract:

Lookup table addressing of a set of lookup tables in an external memory is achieved by: transferring a data word from a compute unit to an input register in a data address generator; providing in at least one deposit-increment index register in the data address generator including a table base field for identifying the location of the set of tables in memory, and a displacement field; and depositing a section of the data word into a displacement field in the index register for identifying the location of a specific entry in the tables.

US Patent:

8458445, Jun 4, 2013

Filed:

Aug 10, 2011

Appl. No.:

13/206644

Inventors:

James Wilson - Foxboro MA, US
Joshua A. Kablotsky - Carlisle MA, US
Yosef Stein - Sharon MA, US
Colm J. Prendergast - Cambridge MA, US
Gregory M. Yukna - Norton MA, US
Christopher M. Mayer - Dover MA, US

Assignee:

Analog Devices Inc. - Norwood MA

International Classification:

G06F 9/44

US Classification:

712225

Abstract:

Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

US Patent:

20050188183, Aug 25, 2005

Filed:

Feb 25, 2004

Appl. No.:

10/786838

Inventors:

James Galeotos - East Taunton MA, US
Christopher Mayer - Dover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F009/00

US Classification:

712225000

Abstract:

Methods and apparatus for handling speculative addresses in a pipelined digital processor are provided. A digital signal processor includes an address generator configured to generate speculative data addresses, a pipelined execution unit configured to execute instructions using data at locations specified by the speculative data addresses, a speculative register file configured to hold the speculative data addresses as corresponding instructions advance through the execution unit, an architectural register file configured to hold architectural data addresses, and control logic configured to write speculative data addresses to the speculative register file as the speculative data addresses are generated by the address generator and to supply speculative data addresses or architectural data addresses to the address generator. The speculative register file may be configured with sufficient capacity to hold one or more architectural data addresses.

US Patent:

20070226469, Sep 27, 2007

Filed:

Mar 6, 2006

Appl. No.:

11/368879

Inventors:

James Wilson - Foxboro MA, US
Joshua Kablotsky - Carlisle MA, US
Yosef Stein - Sharon MA, US
Colm Prendergast - Cambridge MA, US
Gregory Yukna - Norton MA, US
Christopher Mayer - Dover MA, US
John Hayden - Sharon MA, US

International Classification:

G06F 9/44

US Classification:

712225000, 712300000

Abstract:

Accommodating a processor to process a number of different data formats includes loading a data word in a first format from a first storage device; reordering, before it reaches the arithmetic unit, the first format of the data word to a second format compatible with the native order of the arithmetic unit; and vector processing the data word in the arithmetic unit.

US Patent:

20080075376, Mar 27, 2008

Filed:

Sep 26, 2006

Appl. No.:

11/527001

Inventors:

James Wilson - Foxboro MA, US
Joshua A. Kablotsky - Carlisle MA, US
Yosef Stein - Sharon MA, US
Christopher M. Mayer - Dover MA, US

International Classification:

G06K 9/36
G06K 9/46

US Classification:

382247

Abstract:

In a pipeline machine where, in an iterative process, one or more subsequent functions employ one or more parameters determined by one or more antecedent functions and the one or more subsequent functions generate one or more parameters for the one or more antecedent functions, pipeline dependency is reduced by advancing or rotating the iterative process by preliminarily providing to the subsequent function the next one or more parameters on which it is dependent and thereafter: generating by the subsequent function, in response to the one or more parameters on which is it dependent, the next one or more parameters required by the one or more antecedent functions and then, generating by the one or more antecedent functions, in response to the one or more parameters required by the one or more antecedent functions, the next one or more parameters for input to the subsequent function for the next iteration.