Christopher Charles Mcbride

US Patent:

6915443, Jul 5, 2005

Filed:

Jul 13, 2001

Appl. No.:

09/904814

Inventors:

Christopher D. McBride - Tomball TX, US
Paul V. Brownell - Houston TX, US
Timothy R. McJunkin - Idaho Falls ID, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F001/04
G06F001/12
G06F013/00
G11C007/00

US Classification:

713503, 713400, 713401, 713500, 711167, 711170, 36518901, 365194

Abstract:

The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to clock signal path circuits where each circuit has multiple signal paths of varying lengths. By allowing the clock signals to propagate along a particular path, phase lag or time delay is added to those clock signals. Selection of a particular path for the clock signal is made by activating electrically controlled switches which themselves are activated or deactivated by software programs that run during power-up of the computer system that determine required phase lag or time delay of those clock signals as a function of parasitic capacitance in the computer system.

US Patent:

6985365, Jan 10, 2006

Filed:

Sep 28, 2001

Appl. No.:

09/966649

Inventors:

Jeoff M. Krontz - Tomball TX, US
Christopher D. McBride - Austin TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H05K 7/06
H01P 1/18

US Classification:

361777, 361782, 333161, 710306

Abstract:

The system and methods describe a computer system implementing an adjustable control signal path whose length may be precisely adjusted to control timing of a control signal that propagates along the path. One such adjustable signal path has two clusters of possible signal paths. Each of the signal paths in each cluster has a length, and the overall length of the control signal path may be adjusted by selectively implementing one signal path from each of the clusters by electrically connecting that path into the electrical circuit by the selective installation of zero ohm resistors. In this way, a system designer may design several possible signal path lengths on to a motherboard or printed circuit card, and implement the path length which provides the most precise signal timing adjustment.

US Patent:

7017068, Mar 21, 2006

Filed:

Apr 15, 2005

Appl. No.:

11/107044

Inventors:

Christopher D. McBride - Tomball TX, US
Paul V. Brownell - Houston TX, US
Timothy R. McJunkin - Idaho Falls ID, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1/12
G11C 8/00

US Classification:

713401, 713400, 713500, 713503, 365233

Abstract:

The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to clock signal path circuits where each circuit has multiple signal paths of varying lengths. By allowing the clock signals to propagate along a particular path, phase lag or time delay is added to those clock signals. Selection of a particular path for the clock signal is made by activating electrically controlled switches which themselves are activated or deactivated by software programs that run during power-up of the computer system that determine required phase lag or time delay of those clock signals as a function of parasitic capacitance in the computer system.