Christopher D Mills

US Patent:

8438268, May 7, 2013

Filed:

Apr 23, 2008

Appl. No.:

12/108173

Inventors:

Christopher Lee Mills - Wenham MA, US

Assignee:

CA, Inc. - Islandia NY

International Classification:

G06F 15/177
G06F 15/173
H04L 12/28
H04B 7/00

US Classification:

709224, 709222, 370256, 370310

Abstract:

A method and system for prioritizing alerts on end points include an aggregator agent that monitors a plurality of end point agents and receives a signal indicating an out of band operating tolerance from an end point. The aggregator agent locally determines the priority of the received signal based on a rules engine local to the aggregator agent. The aggregator agent transmits the priority of said signal and information associated with said signal to a remote host computer for appropriate handling.

US Patent:

51931583, Mar 9, 1993

Filed:

Oct 18, 1991

Appl. No.:

7/780527

Inventors:

Daryl F. Kinney - Hopkinton MA
Anthony N. Drogaris - Wellesley MA
Christopher H. Mills - Chelmsford MA
Michael Kahaiyan - East Bridgewater MA
John Manton - Marlboro MA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 938
G06F 1516

US Classification:

395375

Abstract:

Method and apparatus for sequentially executing a plurality of pipelined instruction words of a program in which each instruction has independently selectable execution cycle count latencies. After the occurrence of an exception, instructions are identified which began after the instruction that caused the exception, and which have completed execution before execution of the exception provoking instruction was inhibited. Detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Pending instructions, which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor. Pending instructions are subsequently re-executed in the sequence of their occurrence at the time the exception provoking instruction caused the processor to inhibit further instruction execution.