Christopher E Mills

US Patent:

51931583, Mar 9, 1993

Filed:

Oct 18, 1991

Appl. No.:

7/780527

Inventors:

Daryl F. Kinney - Hopkinton MA
Anthony N. Drogaris - Wellesley MA
Christopher H. Mills - Chelmsford MA
Michael Kahaiyan - East Bridgewater MA
John Manton - Marlboro MA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 938
G06F 1516

US Classification:

395375

Abstract:

Method and apparatus for sequentially executing a plurality of pipelined instruction words of a program in which each instruction has independently selectable execution cycle count latencies. After the occurrence of an exception, instructions are identified which began after the instruction that caused the exception, and which have completed execution before execution of the exception provoking instruction was inhibited. Detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Pending instructions, which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor. Pending instructions are subsequently re-executed in the sequence of their occurrence at the time the exception provoking instruction caused the processor to inhibit further instruction execution.