Christopher Lee Morrison

US Patent:

6571375, May 27, 2003

Filed:

May 8, 2000

Appl. No.:

09/566682

Inventors:

Prakash Narain - San Carlos CA
Rajeev K. Ranjan - Santa Clara CA
Christopher R. Morrison - Sunnyvale CA
John M. Beardslee - Menlo Park CA

Assignee:

Real Intent, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 5, 716 4

Abstract:

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, multiple design verification checks associated with a hardware design are linked by determining dependency reationships among the multiple design verification checks. Each of the design verification checks represent a condition that must hold true in order for the hardware design to operate in accordance with an intended flow of logical signals in the hardware design.

US Patent:

6651228, Nov 18, 2003

Filed:

May 8, 2000

Appl. No.:

09/566684

Inventors:

Prakash Narain - San Carlos CA
Rajiv Kumar - Santa Clara CA
John M. Beardslee - Menlo Park CA
Rajeev K. Ranjan - Santa Clara CA
Christopher R. Morrison - Sunnyvale CA

Assignee:

Real Intent, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 5, 716 4

Abstract:

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, hardware design defects can be detected using a novel Intent-Driven Verification process. First, a representation of a hardware design and information regarding the intended flow of logical signals among variables in the representation are received. Then, the existence of potential errors in the hardware design may be inferred based upon the information regarding the intended flow of logical signals by (1) translating the information regarding the intended flow of logical signals into a comprehensive set of checks that must hold true in order for the hardware design to operate in accordance with the intended flow of logical signals, and (2) determining if any of the checks can be violated during operation of circuitry represented by the hardware design.

US Patent:

6704912, Mar 9, 2004

Filed:

Jan 24, 2001

Appl. No.:

09/770068

Inventors:

Prakash Narain - San Carlos CA
Rajeev K. Ranjan - Santa Clara CA
Christopher R. Morrison - Sunnyvale CA
John M. Beardslee - Menlo Park CA

Assignee:

Real Intent, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 4, 716 5, 716 6

Abstract:

A method and apparatus for characterizing information about design attributes is described. The characterization process may begin with determining the dependency among the attributes within a hardware design. Once the dependency is determined, the most relevant information about the hardware design attribute may be highlighted. A user can then focus their attention on the highlighted aspects of the design attribute to draw conclusions about the hardware design as a whole.

US Patent:

6839884, Jan 4, 2005

Filed:

Jan 18, 2001

Appl. No.:

09/766189

Inventors:

Prakash Narain - San Carlos CA, US
Rajeev K. Ranjan - Santa Clara CA, US
Christopher Morrison - Sunnyvale CA, US
John M. Beardslee - Menlo Park CA, US
Rajiv Kumar - Santa Clara CA, US

Assignee:

Real Intent, Inc. - Santa Clara CA

International Classification:

G06F 1750
G06F 945

US Classification:

716 5, 716 4

Abstract:

A method and apparatus are described that facilitate validation of a hardware design having multiple hierarchical levels. In one embodiment, a representation of the hardware design is received, and the hardware design is validated by performing validation processing on a plurality of sub-problems. Each of the plurality of sub-problems covers a computationally feasible size of the hardware design at a corresponding hierarchical level. In another embodiment, validation of a hardware design includes making use of validation processing previously performed with respect to one or more modules included in the hardware design based on the hierarchical relationship between these modules and other modules included in the hardware design.

US Patent:

D513419, Jan 3, 2006

Filed:

Mar 23, 2004

Appl. No.:

29/201901

Inventors:

Christopher S. Morrison - Scottsdale AZ, US
Adam A. Studnicki - Scottsdale AZ, US

Assignee:

Nuvo Hodings, LLC - Scottsdale AZ

International Classification:

1908

US Classification:

D20 28

US Patent:

7088258, Aug 8, 2006

Filed:

Feb 28, 2005

Appl. No.:

10/906646

Inventors:

Christopher S. Morrison - Scottsdale AZ, US

Assignee:

Nuvo Holdings, LLC - Scottsdale AZ

International Classification:

G08B 21/00

US Classification:

340689, 3405455, 340571

Abstract:

A tilt sensor apparatus () includes one or more tilt sensors (). Each tilt sensor () includes a conductive element () entrapped within an opening () formed through a middle planar substrate (). The opening is surrounded by an opening wall () which is entirely covered by a conductor (). A conductive star pattern (′) is formed on a top planar substrate (), and a conductive star pattern (″) is formed on a bottom planar substrate (). The star patterns () are positioned at opposing ends of the opening (). The conductive element moves within the opening () as the apparatus () is tilted. An interrupt-driven control circuit () is configured to indicate a change in orientation only when a short is first detected across a contact pair () that corresponds to an orientation opposite to a currently-indicated orientation.

US Patent:

7109863, Sep 19, 2006

Filed:

Mar 8, 2005

Appl. No.:

10/906806

Inventors:

Christopher S. Morrison - Scottsdale AZ, US

Assignee:

Nuvo Holdings, LLC - Scottsdale AZ

International Classification:

G08B 13/14

US Classification:

3405681, 340429, 343741

Abstract:

Described herein are a transient event detector () comprising electrical circuitry () suitable to detect a transient event, and a container () having a wall with at least two electrically conductive contacts () electrically connected to the electrical circuitry (), each of the at least two electrically conductive contacts () being electrically isolated from each other, and a movable electrically conductive piece () that intermittently connects at least two of the at least two electrically conductive contacts when the electrically conductive piece () is in motion. An RF circuit () couples to a loop antenna () having a tuning capacitor () formed as conductive pads (″) juxtaposed on opposing sides of a planar dielectric substrate (). The tuning capacitor () has a hole () through it, and the hole has a size that is selected to cause the loop antenna () to exhibit a desired resonance frequency.

US Patent:

7190278, Mar 13, 2007

Filed:

Mar 8, 2004

Appl. No.:

10/795720

Inventors:

Christopher S. Morrison - Scottsdale AZ, US

Assignee:

Nuvo Holdings, LLC - Scottsdale AZ

International Classification:

G08B 21/00

US Classification:

340689, 3405455, 340571

Abstract:

Described herein are a transient event detector comprising electrical circuitry suitable to detect a transient event, and a container having a wall with at least two electrically conductive contacts that are electrically connected to the electrical circuitry, each of the at least two electrically conductive contacts being electrically isolated from each other, and a movable electrically conductive piece that intermittently connects at least two of the at least two electrically conductive contacts when the electrically conductive piece is in motion, said movable electrically conducting piece having a mass that is low enough such that if the movable electrically conducting piece is at rest and bridges two of the at least two electrically conductive contacts no transient event is detected by the electrical circuitry, methods of use and methods of manufacture.