Christopher J Myers

US Patent:

59788992, Nov 2, 1999

Filed:

Dec 23, 1997

Appl. No.:

8/997457

Inventors:

Ran Ginosar - Nofit, IL
Rakefet Kol - Haifa, IL
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712210

Abstract:

Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

US Patent:

58983813, Apr 27, 1999

Filed:

Jun 17, 1997

Appl. No.:

8/877526

Inventors:

William J. Gartner - Scottsdale AZ
Christopher R. Myers - Basalt CO

Assignee:

Traffic Technology, Inc. - Scottsdale AZ

International Classification:

G08G 1095

US Classification:

34081565

Abstract:

LED traffic light 30 having a housing 39 that holds at least three different signal lights 32, 34, and 36. The three lights 32, 34, and 36 are each embedded in an opening 50 of housing 39. The LEDs for traffic signal lights 32, 34, and 36 are arranged in symbolic shapes (i. e. universal symbols or words) that further represent one of the traffic signals. Red signal light 32 has red LEDs 31 arranged in an octagon shape (i. e. stop sign shape), and yellow or amber signal light 34 has yellow LEDs 33 arranged in a triangle shape (i. e. caution sign shape). Green signal light 36 has green LEDs 35 arranged in a circular shape. The preferred embodiment is a single lens traffic light 40 having a housing 49 that provides at least three signal lights 42, 44, and 46. The three signal lights 42, 44, and 46 are all embedded in a single opening 50 of housing 49. The LEDs for signal lights 42, 44, and 46 are arranged in a generally common area that allows activation and display of one of the signal lights in a corresponding symbolic shape (i. e.

US Patent:

59419822, Aug 24, 1999

Filed:

Dec 23, 1997

Appl. No.:

8/997461

Inventors:

Ran Ginosar - Nofit, IL
Rakefet Kol - Haifa, IL
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712210

Abstract:

A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.

US Patent:

59480963, Sep 7, 1999

Filed:

Dec 23, 1997

Appl. No.:

8/997462

Inventors:

Ran Ginosar - Nofit, IL
Rakefet Kol - Haifa, IL
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712210

Abstract:

A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

US Patent:

60549327, Apr 25, 2000

Filed:

Nov 20, 1998

Appl. No.:

9/196913

Inventors:

William J. Gartner - Scottsdale AZ
Christopher R. Myers - Basalt CO
Marco Messina - Scottsdale AZ

International Classification:

G08G 1095

US Classification:

34081565

Abstract:

A new embodiment LED traffic light 40 having a housing 49 that provides at least three signal lights 42, 44, and 46. The three signal lights 42, 44, and 46 are all embedded in a single opening 50 of housing 49. The LEDs for signal lights 42, 44, and 46 are arranged in a generally common area that allows activation and display of one of the signal lights in a corresponding symbolic shape (i. e. universal symbol or words). Red signal light 42 has red LEDs 41 spread out and arranged in an octagon shape (i. e. stop sign shape). From a distance or afar, however, it may be difficult for persons to distinguish between the octagon shape and the circular shape (i. e. stop and go signals respectively). Therefore, a border 52 of contrasting color LEDs 54 (i. e. different color other than the color of the octagon) is placed around the octagon shape and illuminated to further enhance and define the stop sign or octagon shape thereof.

US Patent:

59319445, Aug 3, 1999

Filed:

Dec 23, 1997

Appl. No.:

8/996756

Inventors:

Ran Ginosar - Nofit, IL
Rakefet Kol - Haifa, IL
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712239

Abstract:

An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.