Christopher A Nelson

US Patent:

7389408, Jun 17, 2008

Filed:

Dec 1, 2006

Appl. No.:

11/566206

Inventors:

Christopher P. Nelson - Santa Clara CA, US
John Gregory Favor - Scotts Valley CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 7/76

US Classification:

712300

Abstract:

An instruction stream having variable length instructions with embedded constants (e. g. immediate values and displacements) is translated into a stream of operations and a corresponding stream of bit fields, enabling advantageous compact storage of the embedded constants. The operations and the compact constants are optionally stored in entries in a trace cache and/or processed by execution pipelines. The compact constants are optionally formulated as a small constant field, a pointer, or both. The pointer of a particular one of the operations optionally references one of the bit fields within a window of the operations associated with the particular operation. A full-sized constant is constructed from one or more contiguous ones of the bit fields, starting with the referenced bit field, by unpacking and uncompressing information from the contiguous bit fields. An operation optionally includes a plurality of small constant fields and pointers to specify a respective plurality of constants.

US Patent:

7490223, Feb 10, 2009

Filed:

Oct 31, 2006

Appl. No.:

11/555253

Inventors:

John Gregory Favor - Santa Clara CA, US
Christopher P. Nelson - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 15/00
G06F 9/46

US Classification:

712 34, 718108

Abstract:

An apparatus and a method dynamically reassign resources in a coprocessor among master processors that require service from the coprocessor. The method includes each processor, in each processor cycle, keeping track of a number of resource units required for executing operations sent to the coprocessor in that processor cycle and receiving from the coprocessor a number of resource units released during the processor cycle. When the resources need to be reassigned, the coprocessor asserts a signal to the resource yielding processor to cause it to reduce its expectation of resources to zero and ceasing sending service requests to the coprocessor. The coprocessor then moves resources from the yielding processor to the resource receiving processor. Resources are then released to both processors over time to their respective adjusted resource allocations. Such resources may be the number of operations that is allowed to be executing in the coprocessor simulataneously.

US Patent:

7490225, Feb 10, 2009

Filed:

Oct 31, 2006

Appl. No.:

11/555258

Inventors:

John Gregory Favor - Santa Clara CA, US
Christopher P. Nelson - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/38

US Classification:

712216, 712 23, 712217

Abstract:

Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in the processors. An ideal and an external register allocation map are implemented in the coprocessor. When registers are no longer allocated according to the ideal allocation map and the registers are currently allocated according to the external allocation map, the registers are deallocated in the external map and the number of freed registers is reported to the master. The master increments a free register credit count accordingly, and decrements the credit count by one for each operation issued to the coprocessor. An operation is not issued to the coprocessor unless at least a register is free according to the credit count. The master also throttles coprocessor operation issue based on a credit count corresponding to free scheduler entries available in the coprocessor.

US Patent:

7493471, Feb 17, 2009

Filed:

Oct 31, 2006

Appl. No.:

11/555263

Inventors:

John Gregory Favor - Santa Clara CA, US
Christopher P. Nelson - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/34

US Classification:

712 34, 712216, 712217

Abstract:

A method for synchronized renaming between a master processor and a coprocessor includes sending from the master processor an operation for execution by the coprocessor along with an identifier, at the coprocessor, renaming the operation for execution, including assigning a resource and associating the resource with the identifier, and at a subsequent time, sending the identifier from the master processor to the coprocessor to be used in conjunction with the execution of the renamed operation.

US Patent:

7568088, Jul 28, 2009

Filed:

Oct 26, 2006

Appl. No.:

11/553455

Inventors:

John Gregory Favor - Scotts Valley CA, US
Seungyoon Peter Song - San Jose CA, US
Christopher P. Nelson - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/30

US Classification:

712228, 712218

Abstract:

Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flag values at atomic trace boundaries. Checkpointing flags on-demand for atomic traces in a processor system uses a flag checkpoint table to store a plurality of flag checkpoints, each corresponding to an atomic trace. The table is selectively accessed to provide flag information to restore speculative flags when an atomic trace is aborted. A corresponding flag checkpoint is allocated to an invalid state when an atomic trace is renamed. An action that updates flags initializes the corresponding flag checkpoint (if invalid). If the atomic trace is aborted, then the table is searched according to program order starting with the entry corresponding to the aborted atomic trace. The first (if any) valid checkpoint found is used for flag restoration.

US Patent:

7568089, Jul 28, 2009

Filed:

Oct 26, 2006

Appl. No.:

11/553458

Inventors:

John Gregory Favor - Scotts Valley CA, US
Seungyoon Peter Song - San Jose CA, US
Christopher P. Nelson - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/30

US Classification:

712228, 712218

Abstract:

Managing speculative execution via groups of actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flags at trace boundaries. Flag restoration from checkpoints for trace aborts uses a flag checkpoint table to store flag checkpoints, each corresponding to an atomic trace. The table is accessed for flag restoration in response to a trace abort. In a first technique, a corresponding flag checkpoint is stored in response to trace renaming, and the flag checkpoints are updated as flags are modified. Flags are restored from the flag checkpoint corresponding to an aborted atomic trace. In a second technique, a corresponding flag checkpoint is allocated to an invalid state in response to trace renaming, and initialized on-demand when flags are first modified in accordance with the atomic trace. Flags are restored from the oldest flag checkpoint starting from an aborted atomic trace.

US Patent:

7587585, Sep 8, 2009

Filed:

Oct 26, 2006

Appl. No.:

11/553453

Inventors:

John Gregory Favor - Scotts Valley CA, US
Seungyoon Peter Song - San Jose CA, US
Christopher P. Nelson - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/30

US Classification:

712228, 712218

Abstract:

Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flag values at atomic trace boundaries. Checkpointing flags during atomic trace renaming in a processor system uses a flag checkpoint table to store a plurality of flag checkpoints, each corresponding to an atomic trace. The table is selectively accessed to provide flag information to restore speculative flags when an atomic trace is aborted. A corresponding flag checkpoint is stored when an atomic trace is renamed. An action that updates flags updates all entries in the table corresponding to younger atomic traces. If the atomic trace is aborted, then the corresponding flag checkpoint is used for restoration of flag state.

US Patent:

7783863, Aug 24, 2010

Filed:

Oct 24, 2007

Appl. No.:

11/923638

Inventors:

Christopher Patrick Nelson - Santa Clara CA, US
John Gregory Favor - Scotts Valley CA, US
Richard Win Thaik - San Jose CA, US
Matthew William Ashcraft - Belmont CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/00

US Classification:

712220, 712227, 712216, 712207

Abstract:

A method of handling a trace to be aborted includes receiving an indication of a trace to be aborted and an indication of an abort reason corresponding to an execution of the trace to be aborted. The trace to be aborted has a trace type associated therewith and includes a sequence of the operations, and represents a sequence of at least two of the instructions. The method further includes identifying a corrective action based at least in part on the type of the trace to be aborted and on the abort reason, not taking into account a correspondence between the at least one operation that caused the execution to be aborted and the at least one instruction that the at least one operation at least in part represents. A next trace and its trace type is determined for execution, where the determining is based on the trace to be aborted and on the corrective action.