Christopher D Perez

US Patent:

7765511, Jul 27, 2010

Filed:

Oct 22, 2007

Appl. No.:

11/975960

Inventors:

Christopher Perez - Severn MD, US
Arifur Rahman - San Jose CA, US
Christopher H. Kingsley - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
H03K 17/693

US Classification:

716 16, 716 6, 716 4, 716 10, 716 12, 703 19

Abstract:

Various approaches are provided for generating an implementation of an electronic circuit design. In one embodiment, a processor-based method implements a design in an integrated circuit or IC (e. g. , a programmable logic device. The method includes storing performance-variation data that represents location-based performance variations between logically-equivalent-programmable resources of the IC. The respective stored performance-variation data of at least two logically-equivalent-programmable resources of the IC are compared. The logic of the design is mapped, placed and routed on resources of the IC. The mapping, placing and routing includes, for an implementation of at least one subset of the logic of the design, selecting between the at least two logically-equivalent-programmable resources of the IC based on a result of the step of comparing respective stored performance-variation data of the at least two logically-equivalent-programmable resources. An implementation of the design is generated from the logic of the design placed and routed on the resources of the IC.