Christopher E Porter

US Patent:

20180329830, Nov 15, 2018

Filed:

May 11, 2017

Appl. No.:

15/592611

Inventors:

- San Diego CA, US
Christopher Edward Koob - Round Rock TX, US
Gurvinder Singh Chhabra - San Diego CA, US
Andres Alejandro Oportus Valenzuela - San Jose CA, US
Nieyan Geng - San Diego CA, US
Raghuveer Raghavendra - San Diego CA, US
Christopher Porter - Athens GA, US
Anand Janakiraman - San Diego CA, US

International Classification:

G06F 12/1045
G06F 3/06

Abstract:

Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides compressed data regions, corresponding sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the compressed data regions and one of the sets of free memory lists based on a modulus of the virtual address and . The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

US Patent:

20180225224, Aug 9, 2018

Filed:

Feb 7, 2017

Appl. No.:

15/426473

Inventors:

- San Diego CA, US
Christopher Edward Koob - Round Rock TX, US
Gurvinder Singh Chhabra - San Diego CA, US
Andres Alejandro Oportus Valenzuela - San Diego CA, US
Nieyan Geng - San Diego CA, US
Raghuveer Raghavendra - San Diego CA, US
Christopher Porter - Athens GA, US
Anand Janakiraman - San Diego CA, US

International Classification:

G06F 12/128
G06F 12/02

Abstract:

Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.