Christopher M Spence

US Patent:

6356340, Mar 12, 2002

Filed:

Nov 20, 1998

Appl. No.:

09/197020

Inventors:

Christopher A. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03B 2742

US Classification:

355 53, 430 5

Abstract:

A programmable reticle has a plurality of addressable pixels. Each of the pixels has one or more elastic elements which underlie a reflective surface, the elements each being activatable for selectively deforming part of the reflective surface. The amount of deformation is such that light reflected from a deformed part destructively interferes with light reflected from the vicinity of the deformed part. The programmable reticle may be used as a part of a scanning lithography system wherein a wafer or other device to be exposed is moved to expose different of its areas, while the pattern on the programmable reticle is changed to reflect the desired exposure pattern of the area of the wafer currently being exposed. In such a scanning system, any given point on the wafer will be exposed using a number of different pixels on the reticle; therefore the effect of a defective pixel will be âdilutedâ or âvoted outâ by the other, non-defective pixels also involved in exposing that spot.

US Patent:

6437348, Aug 20, 2002

Filed:

Oct 21, 1999

Appl. No.:

09/422310

Inventors:

Christopher F. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

A61N 500

US Classification:

2504912, 2504921

Abstract:

A device for exposing and heating a substrate coated with resist includes an exposure tool for selectively exposing the resist, and a heater for heating the exposed resist, the exposure tool and the heater able to simultaneously act on different portions of the resist. A method of patterning resist on a substrate includes the steps of selectively exposing the resist on the first portion of the substrate, heating the resist on the first portion, and simultaneously or thereafter selectively exposing the resist on a second portion of the substrate. In an exemplary embodiment the exposure tool is an electron beam generator for exposing a chemically-amplified resist, and the heater is a light source such as a laser light source which does not appreciably expose the resist. The device and method allow a post-exposure heating with a smaller delay between the exposure and the heating than with conventional methods, which involve exposing a reticle and mask completely before heating by baking.

US Patent:

6492066, Dec 10, 2002

Filed:

May 28, 1999

Appl. No.:

09/321089

Inventors:

Luigi Capodieci - Sunnyvale CA
Christopher A. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 900

US Classification:

430 5, 716 21

Abstract:

A method ( ) of characterizing optical proximity correction designs includes performing a mathematical transform ( ) on a first feature ( ) and a second feature ( ) each having a core portion ( ) and a first OPC design and a second OPC design applied thereto, respectively. The method ( ) further includes obtaining a metric (162) for the transformed first and second features, wherein the metric is based upon a capability of a pattern transfer system which will utilize masks employing the first and second features ( ) as a patterns thereon. One of the first feature or the second feature is then selected ( ) based upon an application of the metric to the first and second transformed features ( ), thereby selecting the one of the first feature or the second feature which provides for a better pattern transfer performance.

US Patent:

6994939, Feb 7, 2006

Filed:

Oct 29, 2002

Appl. No.:

10/283685

Inventors:

Kouros Ghandehari - Santa Clara CA, US
Jean Y. Yang - Sunnyvale CA, US
Christopher A. Spence - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 9/00

US Classification:

430 5, 430311, 430312, 430320, 430321, 430322, 430323, 430324

Abstract:

A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the second resolution enhancement structure different from the first resolution enhancement structure.

US Patent:

7027130, Apr 11, 2006

Filed:

Apr 28, 2004

Appl. No.:

10/833651

Inventors:

Christopher A. Spence - Sunnyvale CA, US
Todd P. Lukanc - San Jose CA, US
Luigi Capodieci - Santa Cruz CA, US
Joerg Reiss - Sunnyvale CA, US
Sarah N. McGowan - San Francisco CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03B 27/72

US Classification:

355 69

Abstract:

A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.

US Patent:

7120285, Oct 10, 2006

Filed:

Feb 29, 2000

Appl. No.:

09/515348

Inventors:

Christopher A. Spence - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06K 9/46
G06K 9/68

US Classification:

382144

Abstract:

A method of evaluating a wafer structure formation process includes extracting the outline of an actual mask pattern, and simulating a lithographic process using the actual mask pattern to obtain a simulated wafer structure. The extracting the outline of the actual mask pattern may include, for example, imaging the actual mask using a scanning electron microscope (SEM). A second simulated wafer structure may also be obtained, by simulating the lithographic process using the ideal mask pattern design that was used in producing the actual mask pattern. Thus the relative contribution of mask pattern effects to overall wafer proximity effects may be evaluated by comparing the two simulated wafer structures, either with each other or against a benchmark such as a desired, ideal structure. This information may then be used to generate optical proximity correction (OPC) mask designs which compensate for mask patterning errors and give better wafer performance. The simulated wafer structures may be overlaid upon one another to allow for a direct comparison and full analysis of CD variations.

US Patent:

7207017, Apr 17, 2007

Filed:

Jun 10, 2004

Appl. No.:

10/865047

Inventors:

Cyrus Tabery - Santa Clara CA, US
Chris Haidinyak - Santa Cruz CA, US
Todd P. Lukanc - San Jose CA, US
Luigi Capodieci - Santa Cruz CA, US
Carl P. Babcock - Campbell CA, US
Christopher A. Spence - Los Altos CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 4

Abstract:

A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

US Patent:

7657864, Feb 2, 2010

Filed:

Apr 30, 2007

Appl. No.:

11/741845

Inventors:

Cyrus E. Tabery - Santa Clara CA, US
Todd P. Lukanc - San Jose CA, US
Chris Haidinyak - Santa Cruz CA, US
Luigi Capodieci - Santa Cruz CA, US
Carl P. Babcock - Campbell CA, US
Christopher A. Spence - Sunnyvale CA, US

Assignee:

Globalfoundries Inc. - Grand Cayman

International Classification:

G06F 17/50

US Classification:

716 21, 716 19, 716 20, 382144, 430 5, 703 13

Abstract:

A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).