Christopher A Spencer

US Patent:

8468191, Jun 18, 2013

Filed:

Jun 10, 2010

Appl. No.:

12/813074

Inventors:

Michael J. Mantor - Orlando FL, US
Jeffrey T. Brady - Orlando FL, US
Daniel B. Clifton - Chuluota FL, US
Christopher Spencer - Oviedo FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 7/48

US Classification:

708513

Abstract:

Systems and methods for multi-precision computation are disclosed. One embodiment of the present invention includes a plurality of multiply-add units (MADDs) configured to perform one or more single precision operations and an arrangement generator to generate one or more mantissa arrangements using a plurality of double precision numbers. Each MADD is configured to receive and load said mantissa arrangements from the arrangement generator. The MADDs compute a result of a multi-precision computation using the mantissa arrangements. In an embodiment, the MADDs are configured to simultaneously perform operations that include, single precision operations, double-precision additions and double-precision multiply and additions.

US Patent:

8473721, Jun 25, 2013

Filed:

Apr 16, 2010

Appl. No.:

12/762020

Inventors:

Michael J. Mantor - Orlando FL, US
Jeffrey T. Brady - Orlando FL, US
Christopher L. Spencer - Oviedo FL, US
Daniel W. Wong - Cupertino CA, US
Andrew E. Gruber - Arlington MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
ATI Technologies ULC - Markham, Ontario

International Classification:

G06F 9/30

US Classification:

712221, 712300

Abstract:

Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data.

US Patent:

20130003870, Jan 3, 2013

Filed:

Jul 1, 2011

Appl. No.:

13/174873

Inventors:

Philip L. Swan - Richmond Hill, CA
Christopher L. Spencer - Oviedo FL, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA
ATI TECHNOLOGIES ULC - Markham

International Classification:

H04N 7/26

US Classification:

37524026, 375E07026

Abstract:

Methods and apparatus for accelerating the processing of image data are disclosed that are particularly useful in conducting graphical pattern searches. Embodiments of the invention conduct and implement comparative calculations of reference and search image pel data on a multi-pel comparative basis, particularly, sum of the absolute differences (SAD) based calculation comparisons.

US Patent:

20130060829, Mar 7, 2013

Filed:

Sep 1, 2011

Appl. No.:

13/223974

Inventors:

Christopher L. Spencer - Oviedo FL, US
Yun-Xiao Zou - Shanghai, CN
Brian L. Sumner - Sugar Land TX, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 7/38

US Classification:

708440

Abstract:

A method and apparatus for additive range reduction are disclosed. A constant may be pre-stored in a look-up table (LUT), and at least one section of the constant may be retrieved from the LUT for generating a product of an input argument and the constant such that a precision of the product may be controlled in any granularity. For a trigonometric function, 2/π is stored in the LUT, and at least one section of 2/π may be retrieved from the LUT. The argument is multiplied with the retrieved sections of 2/π. The retrieved sections are determined to correctly generate the two least significant bits (LSBs) of an integer portion and a scalable number of most significant bits of the multiplication result. An output of the trigonometric function is generated for the argument with a fractional portion of the multiplication result based on two LSBs of the integer portion of the multiplication result.

US Patent:

20190244323, Aug 8, 2019

Filed:

Feb 2, 2018

Appl. No.:

15/887547

Inventors:

- Cupertino CA, US
Christopher L. Spencer - Chuluota FL, US
Mark D. Earl - Oviedo FL, US
Robert S. Hartog - Windemere FL, US
Timothy M. Kelley - Orlando FL, US

International Classification:

G06T 1/20
G06F 9/30
G06F 9/38

Abstract:

Techniques are disclosed relating to processing groups of graphics work (which may be referred to as “kicks”) using a graphics processing pipeline. In some embodiments, a graphics processor includes multiple sets of configuration registers such that multiple kicks can be processed in the pipeline at the same time. In some embodiments, kicks are pipelined such that a subsequent kick ramps up use of hardware resources as a previous kick winds down. In some embodiments, the graphics processing may execute kicks concurrently and/or preemptively, e.g., based on a priority scheme. In some embodiments, the disclosed techniques may be used with pipelines that include front and back-end fixed function circuitry as well as shared programmable resources such as shader cores. In various embodiments, the disclosed techniques may improve overall performance and/or reduce latency for high-priority graphics tasks.