Christopher A Wade

US Patent:

6440495, Aug 27, 2002

Filed:

Aug 3, 2000

Appl. No.:

09/632497

Inventors:

Christopher P. Wade - Los Gatos CA
Elaine Pao - Los Altos Hills CA
Yaxin Wang - Fremont CA
Jun Zhao - Cupertino CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1606

US Classification:

427250, 42725531, 427255394, 4272557, 427124

Abstract:

The present invention provides a method of depositing ruthenium films on a substrate via liquid source chemical vapor deposition wherein the source material is liquid at room temperature and utilizing process conditions such that deposition of the ruthenium films occurs at a temperature in the kinetic-limited temperature regime. Also provided is a method of depositing a thin ruthenium film on a substrate by liquid source chemical vapor deposition using bis-(ethylcyclopentadienyl) ruthenium by vaporizing the bis-(ethylcyclopentadienyl) ruthenium at a vaporization temperature of about 100-300Â C. to form a CVD source material gas, providing an oxygen source reactant gas and forming a thin ruthenium film on a substrate in a reaction chamber using the CVD source material gas and the oxygen source reactant gas at a substrate temperature of about 100-500Â C.

US Patent:

6479100, Nov 12, 2002

Filed:

Apr 5, 2001

Appl. No.:

09/827878

Inventors:

Xiaoliang Jin - San Jose CA
Christopher P. Wade - Los Gatos CA
Xianzhi Tao - Palo Alto CA
Elaine Pao - Los Altos Hills CA
Yaxin Wang - Fremont CA
Jun Zhao - Cupertino CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1640

US Classification:

42725531, 4272557, 427 99, 4271265, 4273762

Abstract:

The present invention provides a method of forming a ruthenium seed layer on a substrate comprising the steps of introducing a ruthenium-containing compound into a CVD apparatus; introducing oxygen into the CVD apparatus; maintaining an oxygen rich environment in the process chamber for the initial formation of a ruthenium oxide seed layer; vaporizing the ruthenium-containing compound; depositing the ruthenium oxide seed layer onto the substrate by chemical vapor deposition; and annealing the deposited ruthenium oxide seed layer in a gas ambient forming a ruthenium seed layer. Also provided is a method of depositing a ruthenium thin metal film using a metalorganic precursor onto a CVD ruthenium seed layer by metalorganic chemical vapor deposition.

US Patent:

7479685, Jan 20, 2009

Filed:

Mar 10, 2006

Appl. No.:

11/373434

Inventors:

R. Shane Fazzio - Loveland CO, US
Richard C. Ruby - Menlo Park CA, US
Christopher P. Wade - Los Gatos CA, US
Michael Louis Frank - Menlo Park CA, US
David A. Feld - Newark CA, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H01L 29/78

US Classification:

257416, 257245, 333187, 310311, 310324, 310348

Abstract:

An electronic device. The electronic device includes a first electrode and a coating layer. The electronic device is fabricated on a substrate; the substrate has a cavity created in a top surface of the substrate; and the first electrode is electrically coupled to the substrate. The coating layer coats at least part of a substrate surface in the cavity, and the presence of the coating layer results in a mitigation of at least one parasitic leakage path between the first electrode and an additional electrode fabricated on the substrate.

US Patent:

7569424, Aug 4, 2009

Filed:

Nov 15, 2006

Appl. No.:

11/600289

Inventors:

Michael J. Nystrom - San Jose CA, US
Christopher Paul Wade - Los Gatos CA, US
Giles Humpston - Aylesbury, GB

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 21/50
H01L 21/48
H01L 21/44

US Classification:

438119, 438118, 438116

Abstract:

A method of forming a wall structure in a microelectronic assembly includes selectively depositing a flowable material on an upper surface of a first element in the microelectronic assembly, positioning a molding surface in contact with the deposited flowable material and controlling a distance between the upper surface of the first element and the molding surface with one or more objects positioned between the upper surface and the molding surface.

US Patent:

8080854, Dec 20, 2011

Filed:

Dec 22, 2008

Appl. No.:

12/341122

Inventors:

R. Shane Fazzio - Loveland CO, US
Richard C. Ruby - Menlo Park CA, US
Christopher P. Wade - Los Gatos CA, US
Michael Louis Frank - Menlo Park CA, US
David A. Feld - Newark CA, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H01L 29/78

US Classification:

257416, 257245, 333187, 310311, 310324, 310348

Abstract:

An electronic device. The electronic device includes a first electrode and a coating layer. The electronic device is fabricated on a substrate; the substrate has a cavity created in a top surface of the substrate; and the first electrode is electrically coupled to the substrate. The coating layer coats at least part of a substrate surface in the cavity, and the presence of the coating layer results in a mitigation of at least one parasitic leakage path between the first electrode and an additional electrode fabricated on the substrate.

US Patent:

8299626, Oct 30, 2012

Filed:

Aug 16, 2007

Appl. No.:

11/894036

Inventors:

Ilyas Mohammed - Santa Clara CA, US
Belgacem Haba - Saratoga CA, US
Sean Moran - Berlingame CA, US
Wei-Shun Wang - Mountain View CA, US
Ellis Chau - San Jose CA, US
Christopher Wade - Los Gatos CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 21/50

US Classification:

257777, 257686, 257685, 257687, 257690, 257692, 257E2301

Abstract:

A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips.

US Patent:

20030129306, Jul 10, 2003

Filed:

Jul 10, 2002

Appl. No.:

10/193371

Inventors:

Christopher Wade - Los Gatos CA, US
Elaine Pao - Los Altos Hills CA, US
Yaxin Wang - Fremont CA, US
Jun Zhao - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C016/00

US Classification:

427/255280, 427/250000

Abstract:

The present invention provides a method of depositing ruthenium films on a substrate via liquid source chemical vapor deposition wherein the source material is liquid at room temperature and utilizing process conditions such that deposition of the ruthenium films occurs at a temperature in the kinetic-limited temperature regime. Also provided is a method of depositing a thin ruthenium film on a substrate by liquid source chemical vapor deposition using bis-(ethylcyclopentadienyl) ruthenium by vaporizing the bis-(ethylcyclopentadienyl) ruthenium at a vaporization temperature of about 100-300 C. to form a CVD source material gas, providing an oxygen source reactant gas and forming a thin ruthenium film on a substrate in a reaction chamber using the CVD source material gas and the oxygen source reactant gas at a substrate temperature of about 100-500 C.

US Patent:

20080156518, Jul 3, 2008

Filed:

Jan 3, 2007

Appl. No.:

11/649354

Inventors:

Kenneth Allen Honer - Santa Clara CA, US
Christopher Paul Wade - Los Gatos CA, US
Seiichi Tobe - Tokyo, JP
Chung-Chuan Tseng - San Jose CA, US
Ellis Chau - San Jose CA, US
Kyong-Mo Bang - Sunnyvale CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H05K 13/00
H01S 4/00
H05K 1/00

US Classification:

174250, 295921, 29854

Abstract:

A substrate including plural microelectronic device carriers has metallic alignment elements. The alignment elements desirably are disposed in a predetermined positional relationship to terminals on the carriers. The alignment elements are engaged with a carrier frame and a cutting device is aligned with the carrier frame. The cutting device cuts the carriers so that borders of the carriers are in a precise relationship with the terminals.