Chuan L Wang

US Patent:

8354291, Jan 15, 2013

Filed:

Nov 24, 2009

Appl. No.:

12/625543

Inventors:

Chongwu Zhou - Arcadia CA, US
Alexander Badmaev - Pasadena CA, US
Chuan Wang - Los Angeles CA, US

Assignee:

University of Southern California - Los Angeles CA

International Classification:

H01L 21/00

US Classification:

438 57, 438 60, 438478, 257E21009, 257E21411, 257E29268, 257E31011, 257E45002, 977742, 977842, 977843

Abstract:

Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

US Patent:

8618612, Dec 31, 2013

Filed:

Apr 13, 2012

Appl. No.:

13/447105

Inventors:

Chongwu Zhou - Arcadia CA, US
Alexander Badmaev - Pasadena CA, US
Chuan Wang - Los Angeles CA, US

Assignee:

University of Southern California - Los Angeles CA

International Classification:

H01L 21/00

US Classification:

257369, 257E21009, 257E21411, 257E29268, 257E31011, 257E45002, 977742, 977842, 977843

Abstract:

Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

US Patent:

20110101302, May 5, 2011

Filed:

Nov 5, 2010

Appl. No.:

12/940674

Inventors:

Chongwu Zhou - Arcadia CA, US
Chuan Wang - Los Angeles CA, US
Jialu Zhang - Los Angeles CA, US
Alexander Badmaev - Pasadena CA, US
Lewis Gomez De Arco - Los Angeles CA, US

Assignee:

UNIVERSITY OF SOUTHERN CALIFORNIA - Los Angeles CA

International Classification:

H01L 29/775
H01L 21/20
H01L 21/84
H01L 51/52
B82Y 40/00
B82Y 99/00

US Classification:

257 13, 438479, 438151, 438 34, 438156, 257 24, 257E51018, 257E29003, 257E2109, 257E21704, 977936, 977952, 257E29245

Abstract:

Methods, materials, systems and apparatus are described for depositing a separated nanotube networks, and fabricating, separated nanotube thin-film transistors and N-type separated nanotube thin-film transistors. In one aspect, a method of depositing a wafer-scale separated nanotube networks includes providing a substrate with a dielectric layer. The method includes cleaning a surface of the wafer substrate to cause the surface to become hydrophilic. The cleaned surface of the wafer substrate is functionalized by applying a solution that includes linker molecules terminated with amine groups. High density, uniform separated nanotubes are assembled over the functionalized surface by applying to the functionalized surface a separated nanotube solution that includes semiconducting nanotubes.

US Patent:

20120248416, Oct 4, 2012

Filed:

Mar 26, 2012

Appl. No.:

13/430457

Inventors:

Chongwu Zhou - Arcadia CA, US
Alexander Badmaev - Hillsboro OR, US
Chuan Wang - Albany CA, US
Yuchi Che - Los Angeles CA, US

Assignee:

UNIVERSITY OF SOUTHERN CALIFORNIA - Los Angeles CA

International Classification:

H01L 29/786
H01L 29/06
H01L 21/336

US Classification:

257 29, 438197, 257 9, 257E29022, 257E29297, 257E21411

Abstract:

A high performance field-effect transistor includes a substrate, a nanomaterial thin film disposed on the substrate, a source electrode and a drain electrode formed on the nanomaterial thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self-aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proximate the source electrode and the drain electrode in the channel area.

US Patent:

20130119348, May 16, 2013

Filed:

Jun 8, 2012

Appl. No.:

13/492547

Inventors:

Chongwu Zhou - Arcadia CA, US
Alexander Badmaev - Hilsboro OR, US
Chuan Wang - Albany CA, US

International Classification:

H01L 29/775
H01L 29/66

US Classification:

257 29, 438197, 977842, 977938

Abstract:

RF transistors are fabricated at complete wafer scale using a nanotube deposition technique capable of forming high-density, uniform semiconducting nanotube thin films at complete wafer scale, and electrical characterization reveals that such devices exhibit gigahertz operation, linearity, and large transconductance and current drive.

US Patent:

20130134394, May 30, 2013

Filed:

Jan 14, 2013

Appl. No.:

13/740955

Inventors:

University of Southern California - Los Angeles CA, US
Alexander Badmaev - Hillsboro OR, US
Chuan Wang - Albany CA, US

Assignee:

University of Southern California - Los Angeles CA

International Classification:

H01L 21/02
H01L 29/775

US Classification:

257 29, 438479, 977938, 977842

Abstract:

Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

US Patent:

20140070169, Mar 13, 2014

Filed:

Sep 12, 2013

Appl. No.:

14/025511

Inventors:

Chongwu Zhou - Arcadia CA, US
Jialu Zhang - Los Angeles CA, US
Chuan Wang - East Lansing MI, US
Yue Fu - Los Angeles CA, US

International Classification:

H01L 27/32

US Classification:

257 29, 438 23, 977938, 977842

Abstract:

A separated carbon nanotube-based active matrix organic light-emitting diode (AMOLED) device including a substrate and transistors. Each transistor includes an individual back gate patterned on the substrate and a gate dielectric layer disposed over the substrate. An active channel including a network of separated semiconducting nanotubes is disposed over a functionalized surface of the gate dielectric layer. A source contact and a drain contact are formed on two ends of the active channel, with the network of separated nanotubes between the source contact and the drain contact. An organic light-emitting diode (OLED) display device is coupled to the drain of one of the transistors. A system includes a display control circuit having a substrate, with scan lines, data lines, and AMOLED devices formed on the substrate, with each AMOLED device coupled to one of the scan lines and one of the data lines.

US Patent:

20220251614, Aug 11, 2022

Filed:

Apr 22, 2022

Appl. No.:

17/726926

Inventors:

- South San Francisco CA, US
Chuan Wang - South San Francisco CA, US
Jessica Leigh Ochoa - South San Francisco CA, US
Cliff Rutt - South San Francisco CA, US

International Classification:

C12P 13/02
C12N 1/18
C12N 15/81
C12N 15/52
C12P 13/22

Abstract:

Disclosed herein are recombinant host cells and methods capable of producing a tyramine containing hydroxycinnamic acid amide compounds, derivatives and extracts. Some embodiments provided include, for example, consumable products containing the tyramine containing hydroxycinnamic acid amide produced by the recombinant host cells. Some embodiments provided herein are methods for producing a tyramine containing hydroxycinnamic acid amide or hydroxycinnamic acid amide derivative.