Chun Ming Chen

US Patent:

8076199, Dec 13, 2011

Filed:

Feb 13, 2009

Appl. No.:

12/370950

Inventors:

Shenqing Fang - Fremont CA, US
Chun Chen - San Jose CA, US
Wenmei Li - San Jose CA, US
Inkuk Kang - San Jose CA, US
Gang Xue - Sunnyvale CA, US
Hyesook Hong - Allen TX, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438258, 257E21683

Abstract:

A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

US Patent:

8202779, Jun 19, 2012

Filed:

Sep 27, 2010

Appl. No.:

12/891310

Inventors:

Shenqing Fang - Fremont CA, US
Angela Hui - Fremont CA, US
Gang Xue - Sunnyvale CA, US
Alexander Nickel - Santa Clara CA, US
Kashmir Sahota - Fremont CA, US
Scott Bell - San Jose CA, US
Chun Chen - San Jose CA, US
Wai Lo - Palo Alto CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438257, 438197, 257314, 257315

Abstract:

Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

US Patent:

8384146, Feb 26, 2013

Filed:

Mar 23, 2012

Appl. No.:

13/428848

Inventors:

Shenqing Fang - Fremont CA, US
Angela Hui - Fremont CA, US
Gang Xue - Sunnyvale CA, US
Alexander Nickel - Santa Clara CA, US
Kashmir Sahota - Fremont CA, US
Scott Bell - San Jose CA, US
Chun Chen - San Jose CA, US
Wai Lo - Palo Alto CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/76

US Classification:

257314, 257315, 438197, 438257

Abstract:

Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

US Patent:

8441063, May 14, 2013

Filed:

Dec 30, 2010

Appl. No.:

12/982006

Inventors:

Shenqing Fang - Fremont CA, US
Tung-Sheng Chen - Cupertino CA, US
Chun Chen - San Jose CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/792
H01L 21/336

US Classification:

257324, 257E29309, 257E21423, 257E2121, 257E21679, 438287, 438954

Abstract:

A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.

US Patent:

8637918, Jan 28, 2014

Filed:

Nov 10, 2011

Appl. No.:

13/294098

Inventors:

Shenqing Fang - Fremont CA, US
Chun Chen - San Jose CA, US
Wenmei Li - San Jose CA, US
Inkuk Kang - San Jose CA, US
Gang Xue - Sunnyvale CA, US
Hyesook Hong - Allen TX, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/792

US Classification:

257324, 257326

Abstract:

A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

US Patent:

20130208000, Aug 15, 2013

Filed:

Feb 10, 2012

Appl. No.:

13/371292

Inventors:

Aylin Uysal - San Francisco CA, US
Sally Baggett - Healdsburg CA, US
Chun Yi Chen - Belmont CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G09G 5/00

US Classification:

345629, 345676, 345660

Abstract:

A system and method for facilitating selectively displaying data. An example method includes organizing data into one or more data objects represented by one or more graphical display elements; displaying the one or more graphical display elements in a band of plural display elements; and providing a first user option to simultaneously adjust spacing between each of the plural display elements in the band. In a specific embodiment, the method further includes providing user options to convert the band of display elements into a carousel view or to a filmstrip view by adjusting the spacing, and to switch between display of graphical display elements in a grid and display of graphical display elements in the band.

US Patent:

20210221850, Jul 22, 2021

Filed:

Jun 6, 2019

Appl. No.:

15/734877

Inventors:

- Oakland CA, US
Chun Chieh Chen - Oakland CA, US
Marie Stark - Oakland CA, US

International Classification:

C07K 14/005
C12N 7/00
C07K 14/62

Abstract:

A Hepatitis E virus (HEV)-based virus like nanoparticle (HEVNP) made with a modified capsid protein containing at least a portion of open reading frame 2 (ORF2) protein conjugated with gold nanocluster is provided. Also provided are methods of targeted delivery of a nucleic acid using the HEVNP.

US Patent:

20210147526, May 20, 2021

Filed:

Nov 13, 2020

Appl. No.:

17/098199

Inventors:

- South San Francisco CA, US
Chun Chen - Albany CA, US
Scott Turner - Oakland CA, US

International Classification:

C07K 16/18
A61K 45/06
A61P 25/28

Abstract:

Disclosed herein are pharmaceutical agents and compositions that activate integrin heterodimers that contain beta-1 integrin protein that specifically bind laminin protein. Such agents and compositions are useful for treating diseases related to muscle malfunction, including muscular dystrophies.