Chun K Ng

age ~76

from Camas, WA

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Also known as:

Chun Kit Ng
Chun Betsy Ng
Kit Ng
Kit Ng Chun
Chunkit K Ng
Chun-Kit Ng
Ng Chun Kit
Ng Chun-Kit

Connected to:

Chun Ng Phones & Addresses

Camas, WA
9130 NW Leahy Rd, Portland, OR 97229 • (503)8047100
Forest Grove, OR
Paducah, KY
12775 NW Creekside Dr, Portland, OR 97229 • (503)6909666

Work

Position:

Food Preparation and Serving Related Occupations

Education

Degree:

High school graduate or higher

Resumes

Chun Ng

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Industry:

Biotechnology

Education:

Michigan State University 2009 - 2014
Bachelors, Chemical Engineering, Biology

Languages:

English
Mandarin

Management Trainee

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Industry:

Logistics And Supply Chain

Work:

Modern Terminals
Management Trainee

It Technician

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Work:

It Technician

Chun Ng

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Chun Ng

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Chun Ng

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Location:

United States

Medicine Doctors

Chun L. Ng

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Specialties:

Emergency Medicine

Work:

IU Health PhysiciansIndiana University Health West Emergency
1111 Ronald Reagan Pkwy, Avon, IN 46123
(317)2173500 (phone), (317)2173551 (fax)

Education:

Medical School
University of Tennessee College of Medicine at Memphis
Graduated: 1995

Procedures:

Vaccine Administration
Lumbar Puncture

Conditions:

Skin and Subcutaneous Infections
Abdominal Hernia
Abnormal Vaginal Bleeding
Acne
Acute Bronchitis

Languages:

English
Spanish

Description:

Dr. Ng graduated from the University of Tennessee College of Medicine at Memphis in 1995. He works in Avon, IN and specializes in Emergency Medicine.

Chun F. Ng

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Specialties:

Hematology/Oncology

Work:

Kaiser Permanente Medical Group
7373 West Ln, Stockton, CA 95210
(209)4762000 (phone), (209)4763012 (fax)

Education:

Medical School
New York Medical College
Graduated: 2006

Conditions:

Malignant Neoplasm of Female Breast
Multiple Myeloma
Non-Hodgkin's Lymphoma

Languages:

English

Description:

Dr. Ng graduated from the New York Medical College in 2006. He works in Stockton, CA and specializes in Hematology/Oncology.

Chun J. Ng

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Specialties:

General Practice

Work:

SCOSI Orthopedics
18575 Gale Ave STE 278, Rowland Heights, CA 91748
(626)9653880 (phone), (714)7982366 (fax)

Languages:

Chinese
English
Spanish

Description:

Mr. Ng works in City of Industry, CA and specializes in General Practice. Mr. Ng is affiliated with Placentia Linda Hospital and Whittier Hospital Medical Center.

Chun Fai Ng

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Specialties:

Internal Medicine
Hematology & Oncology

Education:

New York Medical College (2006)

Us Patents

Method And System For Debugging Using Replicated Logic
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US Patent:

6904576, Jun 7, 2005
Filed:

Aug 9, 2002
Appl. No.:

10/215869
Inventors:

Chun Kit Ng - Portland OR, US
Kenneth S. McElvain - Los Altos CA, US
Assignee:

Synplicity, Inc. - Sunnyvale CA
International Classification:

G06F017/50
US Classification:

716 4, 716 5, 716 7, 716 18
Abstract:

A method and apparatus is provided to debug using replicated logic. A text representation of a circuit is compiled to generate a first register transfer level (RTL) netlist. The netlist may be mapped to a target architecture, such as a field programmable gate array (FPGA). The netlist may be used to program an FPGA to create a prototype board for debugging. After debug, a portion of the circuit that a designer would like to analyze is selected. The selected portion of the circuit is replicated. Delay logic is inserted to delay the inputs into the replicated portion of the circuit. The text representation of the circuit is recompiled to generate a second RTL netlist. The second RTL netlist may be mapped to a target architecture, such as a FPGA or application specific integrated circuit (ASIC).

Method And System For User-Defined Triggering Logic In A Hardware Description Language
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US Patent:

7107570, Sep 12, 2006
Filed:

Apr 8, 2004
Appl. No.:

10/822192
Inventors:

Mario Larouche - Portland OR, US
Chun Kit Ng - Portland OR, US
Assignee:

Synplicity, Inc. - Sunnyvale CA
International Classification:

G06F 17/50
G06F 11/00
US Classification:

716 18, 716 4, 703 16, 714 30
Abstract:

A method and system for user-defined triggering logic in a hardware description language is described. The method includes reading a file containing user-defined triggering logic described in a hardware description language (HDL), inserting and connecting the triggering logic to a circuit described in HDL, and compiling the HDL description of the circuit to generate a register transfer level (RTL) netlist.

Method And System For Debugging Using Replicated Logic And Trigger Logic
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US Patent:

7213216, May 1, 2007
Filed:

Apr 22, 2005
Appl. No.:

11/112092
Inventors:

Chun Kit Ng - Portland OR, US
Mario Larouche - Portland OR, US
Assignee:

Synplicity, Inc. - Sunnyvale CA
International Classification:

G06F 17/50
US Classification:

716 3, 716 1, 716 4, 716 6, 716 18
Abstract:

A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

Method And System For Debug And Test Using Replicated Logic
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US Patent:

7398445, Jul 8, 2008
Filed:

Aug 2, 2005
Appl. No.:

11/195180
Inventors:

Chun Kit Ng - Portland OR, US
Mario Larouche - Portland OR, US
Assignee:

Synplicity, Inc. - Sunnyvale CA
International Classification:

G06F 11/00
US Classification:

714741, 714 11, 714 21, 714 25, 714 37, 714 45, 714724, 714729, 714734, 703 13, 703 15, 703 19, 703 22, 716 4, 716 5, 716 6
Abstract:

A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded. This recorded data may then used to generate a test to be run on a software simulator when the circuit is modified.

Method And System For Debugging Using Replicated Logic And Trigger Logic
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US Patent:

7665046, Feb 16, 2010
Filed:

Apr 3, 2007
Appl. No.:

11/732784
Inventors:

Chun Kit Ng - Portland OR, US
Kenneth S. McElvain - Los Altos CA, US
Assignee:

Synopsys, Inc. - Mountain View CA
International Classification:

G06F 17/50
US Classification:

716 1, 716 4, 716 5, 716 6, 716 18, 703 13, 703 14
Abstract:

A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

Method And Apparatus For Determining A Phase Relationship Between Asynchronous Clock Signals
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US Patent:

7904859, Mar 8, 2011
Filed:

May 8, 2008
Appl. No.:

12/117714
Inventors:

Richard C. Maixner - West Linn OR, US
Mario Larouche - Portland OR, US
Chun Kit Ng - Portland OR, US
Kenneth S. McElvain - Menlo Park CA, US
Assignee:

Synopsys, Inc. - Mountain View CA
International Classification:

G06F 17/50
US Classification:

716105, 716103, 716104, 327161, 703 14
Abstract:

Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time, and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.

Techniques For Use With Automated Circuit Design And Simulations
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US Patent:

7908574, Mar 15, 2011
Filed:

May 8, 2008
Appl. No.:

12/117711
Inventors:

Mario Larouche - Portland OR, US
Richard C. Maixner - West Linn OR, US
Chun Kit Ng - Portland OR, US
Kenneth S. McElvain - Menlo Park CA, US
Assignee:

Synopsys, Inc. - Mountain View CA
International Classification:

G06F 17/50
US Classification:

716100, 716 1
Abstract:

Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described.

Method And System For Debug And Test Using Replicated Logic
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US Patent:

7962869, Jun 14, 2011
Filed:

Jul 1, 2008
Appl. No.:

12/166298
Inventors:

Chun Kit Ng - Portland OR, US
Mario Larouche - Portland OR, US
Assignee:

Synopsys, Inc. - Mountain View CA
International Classification:

G06F 9/455
G06F 17/50
US Classification:

716106, 716100, 716101, 716104, 716107, 716108, 716111, 716112, 716113
Abstract:

A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded. This recorded data may then used to generate a test to be run on a software simulator when the circuit is modified.