Chun C Yu

US Patent:

6982713, Jan 3, 2006

Filed:

Jan 13, 2003

Appl. No.:

10/341842

Inventors:

Pingping Shao - Sunnyvale CA, US
Jianbo Zhang - Sunnyvale CA, US
Guofang Jiao - Sunnyvale CA, US
Chun Yu - Sunnyvale CA, US
Linglan Zhang - Sunnyvale CA, US
Jinshan Zheng - Shanghai, CN

Assignee:

XGI Technology Inc. - Hsinchu

International Classification:

G06T 15/40

US Classification:

345422

Abstract:

A method and system for clearing depth and color buffers in a real time graphics rendering system. The method and system are able to improve both depth and color buffer clearing. The method and system may utilize a frame flag, a depth clearing module, and a fast color and frame flag clearing module. The system assigns a frame flag to each pixel, which is used to determine whether the current Z value for the pixel is valid. The frame flag may be attached to Z value in the depth buffer. Instead of filling entire depth and color buffers with background values, the system only fills the holes that were not drawn in the previous frame. The fast color and frame flag clearing module traverses a rectangular area, tile by tile, where a tile is a block of pixels, to determine whether each pixel is background by checking the frame flags that are read from the depth buffer. If at least one pixel of a tile is background, the module updates those pixels' color with background color by sending requests to memory interface.

US Patent:

20200273142, Aug 27, 2020

Filed:

Feb 21, 2019

Appl. No.:

16/282003

Inventors:

- San Diego CA, US
Tao Wang - Sunnyvale CA, US
Shangmei Yu - Sunnyvale CA, US
Jing Gao - San Jose CA, US
Jian Liang - San Diego CA, US
Andrew Evan Gruber - Arlington MA, US
Chun Yu - Rancho Santa Fe CA, US

International Classification:

G06T 1/60
G06F 3/06

Abstract:

The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.

US Patent:

20200020067, Jan 16, 2020

Filed:

Jul 13, 2018

Appl. No.:

16/035372

Inventors:

- San Diego CA, US
Tao WANG - Sunnyvale CA, US
Chun YU - Rancho Santa Fe CA, US
Andrew Evan GRUBER - Arlington MA, US
Donghyun KIM - San Diego CA, US
Nigel POOLE - West Newton MA, US
Tzun-Wei LEE - San Jose CA, US
Shambhoo KHANDELWAL - Santa Clara CA, US

International Classification:

G06T 1/20
G06T 15/00
G06T 1/60

Abstract:

A method, an apparatus, and a computer-readable medium may be configured to perform a binning pass for a first frame. The apparatus may be configured to perform a rendering pass for the first frame in parallel with the binning pass. The apparatus may be configured to enhance efficiency in performing a binning pass and a rendering pass for tile-based rendering, such that the binning pass and rendering pass are performed concurrently. The apparatus may be configured to perform the binning pass using a first hardware pipeline, and may be configured to perform the rendering pass using a second hardware pipeline.