Chung Lin Wang

US Patent:

7376477, May 20, 2008

Filed:

Dec 20, 2001

Appl. No.:

10/036966

Inventors:

Dave B. Adair - Huntington Beach CA, US
James V. Burrell - Denver CO, US
Charles Chao - Bellflower CA, US
Mohan K. Gupta - Torrance CA, US
Melissa Hirota - Long Beach CA, US
Patrick Jaillet - Lexington MA, US
Lalit Jain - Cerritos CA, US
John Kealoha, III - Long Beach CA, US
Ryan K. Kita - Irvine CA, US
Quang N. Mai - Huntington Beach CA, US
Dirk Niemeyer - Foothill Ranch CA, US
Nirod N. Samal - Costa Mesa CA, US
Chung Wang - Hacienda Heights CA, US
Flora F. Wang - Cerritos CA, US
Andrea L. Whobrey - Torrance CA, US

Assignee:

Honda Motor Co., Ltd. - Tokyo

International Classification:

G06Q 10/00
G06Q 90/00
G06F 17/50

US Classification:

700 95, 705 7, 705 8, 705 28, 705 29, 700 97, 700 99

Abstract:

A method and system for allowing a vehicle dealer and manufacturer to match dealer orders and manufacturing plant shipments easily and equitably are disclosed. The method significantly decreases processing time, saving valuable time, money, and manpower resources. An automated linear expression calculation for determining and balancing vehicle allocation allows for equitable balancing of manufacturing plant orders and efficient optimization. The linear expression calculation may be performed in an iterative series of steps. The linear expression calculation handles a plurality of attribute features, thereby accommodating a plurality of dealer requests and vehicle options. The linear expression calculation creates a matrix representing the plurality of attribute features, and with each iteration the values within the matrix are refined and optimized, with the resulting matrix representing an optimized and balanced allocation of manufacturing plant production orders among a plurality of manufacturing plants.

US Patent:

7791170, Sep 7, 2010

Filed:

Jul 10, 2006

Appl. No.:

11/456291

Inventors:

Shang-Yi Chiang - Los Altos CA, US
Chung Wang - Fremont CA, US
Shou-Gwo Wuu - Hsin-Chu, TW
Dun-Nian Yaung - Taipei, TW

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu

International Classification:

H01L 25/065

US Classification:

257549, 257544, 257E21544

Abstract:

The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the back surface; and an aluminum doped feature formed in the substrate and disposed horizontally between two adjacent elements of the plurality of sensor elements and vertically between the back surface and the plurality of sensor elements.

US Patent:

7930051, Apr 19, 2011

Filed:

Apr 23, 2008

Appl. No.:

12/108407

Inventors:

David B. Adair - Huntington Beach CA, US
James V. Burrell - Denver CO, US
Charles Chao - Bellflower CA, US
Mohan K. Gupta - Torrance CA, US
Melissa Hirota - Long Beach CA, US
Patrick Jaillet - Lexington MA, US
Lalit Jain - Cerritos CA, US
John Kealoha, III - Long Beach CA, US
Ryan K. Kita - Irvine CA, US
Quang N. Mai - Huntington Beach CA, US
Dirk Niemeyer - Foothill Ranch CA, US
Nirod Samal - Costa Mesa CA, US
Chung Wang - Hacienda Heights CA, US
Flora F. Wang - Cerritos CA, US
Andrea L. Whobrey - Torrance CA, US

Assignee:

Honda Motor Co., Ltd. - Tokyo

International Classification:

G06F 19/00
G06F 15/02
G06F 17/50
G06F 9/46
G06F 9/44
G05B 19/418
G06Q 10/00
A01K 5/02

US Classification:

700100, 700 95, 700 96, 700 97, 700 99, 700101, 705 7, 705 8, 705 9, 705 28, 705 29

Abstract:

A method and system for allowing a vehicle dealer and manufacturer to match dealer orders and manufacturing plant shipments easily and equitably are disclosed. The method significantly decreases processing time, saving valuable time, money, and manpower resources. An automated linear expression calculation for determining and balancing vehicle allocation allows for equitable balancing of manufacturing plant orders and efficient optimization. The linear expression calculation may be performed in an iterative series of steps. The linear expression calculation handles a plurality of attribute features, thereby accommodating a plurality of dealer requests and vehicle options. The linear expression calculation creates a matrix representing the plurality of attribute features, and with each iteration the values within the matrix are refined and optimized, with the resulting matrix representing an optimized and balanced allocation of manufacturing plant production orders among a plurality of manufacturing plants.

US Patent:

8148223, Apr 3, 2012

Filed:

May 22, 2006

Appl. No.:

11/437673

Inventors:

Yi-Ching Lin - Sunnyvale CA, US
Chun-Yao Chen - Hsinchu, TW
Chen-Jong Wang - Hsinchu, TW
Shou-Gwo Wuu - Hsinchu, TW
Chung S. Wang - Fremont CA, US
Chien-Hua Huang - Hsinchu, TW
Kun-Lung Chen - Taipei, TW
Ping Yang - Kaohsiung, TW

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu

International Classification:

H01L 21/8242

US Classification:

438253, 438244, 438254, 438397, 257303, 257308, 257E21619

Abstract:

Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

US Patent:

7994032, Aug 9, 2011

Filed:

Jul 28, 2010

Appl. No.:

12/845496

Inventors:

Shang-Yi Chiang - Los Also CA, US
Chung Wang - Fremont CA, US
Shou-Gwo Wuu - Hsin-Chu, TW
Dun-Nian Yaung - Taipei, TW

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu

International Classification:

H01L 21/38

US Classification:

438558, 257544, 257549, 257E21544, 257E25005, 257E27124

Abstract:

The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the back surface; and an aluminum doped feature formed in the substrate and disposed horizontally between two adjacent elements of the plurality of sensor elements and vertically between the back surface and the plurality of sensor elements.

US Patent:

20120139022, Jun 7, 2012

Filed:

Feb 9, 2012

Appl. No.:

13/369894

Inventors:

Yi-Ching Lin - Sunnyvale CA, US
Chun-Yao Chen - Hsinchu, TW
Chen-Jong Wang - Hsinchu, TW
Shou-Gwo Wuu - Hsinchu, TW
Chung S. Wang - Fremont CA, US
Chien-Hua Huang - Hsinchu, TW
Kun-Lung Chen - Taipei, TW
Ping Yang - Kaohsiung, TW

International Classification:

H01L 29/92
H01L 27/108

US Classification:

257301, 257532, 257E29342, 257E27084

Abstract:

Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

US Patent:

52273202, Jul 13, 1993

Filed:

Sep 10, 1991

Appl. No.:

7/757412

Inventors:

Eric A. Johnson - San Jose CA
Ying T. Loh - Saratoga CA
Yoshiko H. Strunk - Sunnyvale CA
Chung S. Wang - Fremont CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 21335

US Classification:

437 44

Abstract:

A method produces a transistor with an overlapping gate. A first gate region is placed on a substrate between two source/drain regions. The first gate region includes a polysilicon region on top of a dielectric region. Gate overlap regions are placed around the polysilicon region. The gate overlap regions extend out over the two source/drain regions. The gate overlap regions are formed of a metal-silicide layer, for example Titanium-silicide. A top portion of the metal-silicide layer is oxidized to form a silicon dioxide layer on top of the metal-silicide layer. At the time of oxidation, the metal-silicide layer is also annealed to which further helps to improves the Titanium-silicide stoichiometry.

US Patent:

52886522, Feb 22, 1994

Filed:

Dec 18, 1992

Appl. No.:

7/993229

Inventors:

Chung S. Wang - Fremont CA
Edward D. Nowak - Pleasanton CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 21265
H01L 2970

US Classification:

437 31

Abstract:

A bipolar transistor is fabricated in a CMOS-compatible process with a laterally graded emitter structure that is fabricated in a "top-down" implant process. The laterally graded emitter decreases electric field intensities in the emitter-base junction under reverse bias, thus reducing hot carrier generation and improving emitter-base junction breakdown voltage. High current gain is further maintained by establishing sharply defined emitter-base junctions. During fabrication a blocking layer and overlying cap layer are formed in an inverted "T" shape over a desired emitter window region. Lateral projection of the cap ledges are used to define the laterally graded emitter width, while the distance separating the cap ledges defines the width of the central emitter region. The central emitter region is implanted and driven-in to a desired depth, after which the protective cap is removed. The entire emitter window region is then implanted with a like polarity dopant of lesser dosage, which dopant is then driven-in to form laterally graded emitter junctions of a desired depth.