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Chung-Peng Ho

age ~69

from Austin, TX

Chung-Peng Ho Phones & Addresses

  • 11704 Lemens Sugar Cv, Austin, TX 78750 • (512)3360739

Us Patents

  • Method And System For Drying A Substrate

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  • US Patent:
    7070915, Jul 4, 2006
  • Filed:
    Aug 29, 2003
  • Appl. No.:
    10/650729
  • Inventors:
    Chung-Peng Ho - Austin TX, US
    Kathleen Nafus - Austin TX, US
    Kaz Yoshioka - Austin TX, US
    Richard Yamaguchi - Gilbert AZ, US
  • Assignee:
    Tokyo Electron Limited - Tokyo
  • International Classification:
    G03C 5/00
  • US Classification:
    430322, 430330, 430329, 355 67, 355 72
  • Abstract:
    A method and system is described for drying a thin film on a substrate following liquid immersion lithography. Drying the thin film to remove immersion fluid from the thin film is performed prior to baking the thin film, thereby reducing the likely hood for interaction of immersion fluid with the baking process. This interaction has been shown to cause non-uniformity in critical dimension for the pattern formed in the thin film following the developing process.
  • Method And System For Drying A Substrate

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  • US Patent:
    7582414, Sep 1, 2009
  • Filed:
    May 26, 2006
  • Appl. No.:
    11/441154
  • Inventors:
    Chung-Peng Ho - Austin TX, US
    Kathleen Nafus - Austin TX, US
    Kaz Yoshioka - Austin TX, US
    Richard Yamaguchi - Gilbert AZ, US
  • Assignee:
    Tokyo Electron Limited - Tokyo
  • International Classification:
    G03B 27/52
  • US Classification:
    430322, 430330, 430329, 355 67, 355 72
  • Abstract:
    A method and system is described for drying a thin film on a substrate following liquid immersion lithography. Drying the thin film to remove immersion liquid from the thin film is performed prior to baking the thin film, thereby reducing the likely hood for interaction of immersion liquid with the baking process. This interaction has been shown to cause non-uniformity in critical dimension for the pattern formed in the thin film following the developing process.
  • Method For Patterning Resist

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  • US Patent:
    20020136992, Sep 26, 2002
  • Filed:
    Mar 26, 2001
  • Appl. No.:
    09/817408
  • Inventors:
    Chung-Peng Ho - Austin TX, US
    Bernard Roman - Austin TX, US
  • International Classification:
    G03F007/20
  • US Classification:
    430/397000, 430/311000, 430/322000, 430/396000
  • Abstract:
    A resist layer () on a semiconductor wafer () is patterned by using a scanning exposure system () which provides light, containing pattern information which is intended to be transferred to the wafer. The lithographic system is a step and scan system in which a reticle () passes between a light source and a lens system(). The wafer with the resist layer is passed through a focal plane of the patterned light at a tilt angle (). The user selects a desirable range for the depth of the resist to be exposed at the focus of the patterned light. The tilt angle is calculated by taking the arc tangent of the desirable range divided by a width of a slit region () of the projected light. The depth of focus increases over standard step and scan techniques.

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