Cindy R Simpson

US Patent:

6500324, Dec 31, 2002

Filed:

May 1, 2000

Appl. No.:

09/561776

Inventors:

Cindy Reidsema Simpson - Austin TX
Matthew T. Herrick - Austin TX
Gregory S. Etherington - Cedar Creek TX
James Derek Legg - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

C25D 712

US Classification:

205 96, 205103, 205123, 205128, 205145, 205157, 205223

Abstract:

An electroplating system ( ) and process makes electrical current density across, a semiconductor device substrate ( ) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers ( and ) reduce the electrical current density near the edge of the substrate ( ). By reducing the current density near the edge of the substrate ( ), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate ( ). The system can also be modified so that the material that electrical current density modifier portions ( ) on structures ( ) can be removed without having to disassemble any portion of the head ( ) or otherwise remove the structures ( ) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

US Patent:

6686282, Feb 3, 2004

Filed:

Mar 31, 2003

Appl. No.:

10/403967

Inventors:

Cindy Simpson - Austin TX
Hsing H. Tseng - Austin TX
Olubunmi O. Adetutu - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2144

US Classification:

438685, 438648, 438656, 438683, 438686, 257750, 257761, 257763, 257764

Abstract:

Using plating, metal gates for N channel and P channel transistors are formed of different materials to achieve the appropriate work function for these N and P channel transistors. The plating is achieved with a seed layer consistent with the growth of the desired layer. The preferred materials are selected from the platinum metals, which comprise ruthenium, ruthenium oxide, iridium, palladium, platinum, nickel, osmium, and cobalt. These are attractive metals because they are relatively high conductivity, can be plated, and provide a good choice of work functions for forming P and N channel transistors.

US Patent:

7323094, Jan 29, 2008

Filed:

Aug 14, 2002

Appl. No.:

10/218810

Inventors:

Cindy Reidsema Simpson - Austin TX, US
Matthew T. Herrick - Austin TX, US
Gregory S. Etherington - Cedar Creek TX, US
James Derek Legg - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

C25D 5/48
C25D 7/12
C25D 21/00

US Classification:

205 80, 205 96, 205103, 205123, 205128, 205145, 205157, 205223

Abstract:

An electroplating system () and process makes electrical current density across a semiconductor device substrate () surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers ( and ) reduce the electrical current density near the edge of the substrate (). By reducing the current density near the edge of the substrate (), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (). The system can also be modified so that the material that plates on electrical current density modifier portions () of structures () can be removed without having to disassemble any portion of the head () or otherwise remove the structures () from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

US Patent:

63163594, Nov 13, 2001

Filed:

Feb 4, 2000

Appl. No.:

9/498613

Inventors:

Cindy Reidsema Simpson - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 2144
H01L 214763

US Classification:

438678

Abstract:

In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).

US Patent:

60225963, Feb 8, 2000

Filed:

Jul 17, 1996

Appl. No.:

8/684280

Inventors:

Thomas H. Baum - New Fairfield CT
Luis J. Matienzo - Endicott NY
Cindy Reidsema Simpson - Austin TX
Joseph E. Varsik - Binghamton NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

B05D 300
B05D 306
B05D 512
B05D 304

US Classification:

427555

Abstract:

A method is provided for selectively metallizing one or more three-dimensional materials in an electronic circuit package comprising the steps of forming a layer of seeding solution on a surface of the three-dimensional material of interest, exposing this layer to light of appropriate wavelength, resulting in the formation of metal seed on regions of the three-dimensional material corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e. g. , plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper. Of additional significance, this method is ideal for plating three-dimensional materials such as cone-shaped connectors used in electronic circuit packages.

US Patent:

60872586, Jul 11, 2000

Filed:

Dec 12, 1996

Appl. No.:

8/764001

Inventors:

Logan Lloyd Simpson - Austin TX
Cindy Reidsema Simpson - Austin TX
Joseph Edward Varsik - Binghamton NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438678

Abstract:

A method for selectively metallizing one or more through-holes, other openings (such as slots), or edges of an electronic circuit package comprising the steps of forming a layer of seeding solution on a drilled surface of a substrate of interest exposing this layer to light of appropriate wavelength, through a mask that does not completely cover the through-holes or openings and thereby results in the formation of metal seed on regions of the substrate surface corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e. g. , plated, onto the metal seed using conventional techniques.

US Patent:

62183028, Apr 17, 2001

Filed:

Jul 21, 1998

Appl. No.:

9/121068

Inventors:

Gregor Braeckelmann - Austin TX
Ramnath Venkatraman - Austin TX
Matthew Thomas Herrick - Austin TX
Cindy R. Simpson - Austin TX
Robert W. Fiordalice - Austin TX
Dean J. Denning - Del Valle TX
Ajay Jain - Austin TX
Cristiano Capasso - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 2144

US Classification:

438687

Abstract:

An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.

US Patent:

62971557, Oct 2, 2001

Filed:

May 3, 1999

Appl. No.:

9/305093

Inventors:

Cindy Reidsema Simpson - Austin TX
Robert Douglas Mikkola - Austin TX
Matthew T. Herrick - Austin TX
Brett Caroline Baker - Austin TX
David Moralez Pena - Buda TX
Edward Acosta - San Marcos TX
Rina Chowdhury - Austin TX
Marijean Azrak - Austin TX
Cindy Kay Goldberg - Austin TX
Mohammed Rabiul Islam - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 2144

US Classification:

438687

Abstract:

A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.

Address:

20700 Cameron Rd, Coupland, TX 78615

VIN:

JTEZU17R970086324

Make:

TOYOTA

Model:

4RUNNER

Year:

2007