Clarence J Lewis

US Patent:

59036010, May 11, 1999

Filed:

Dec 17, 1996

Appl. No.:

8/768249

Inventors:

Khodor S. Elnashar - Dallas TX
Mahmoud M. Yazdani - Allen TX
Clarence D. Lewis - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F1/32

US Classification:

375220

Abstract:

A power reduction system for a UART system having a controllable oscillator for producing free-running clock signals. A controlled clock synchronizer having an output terminal is coupled to the oscillator and responsive to both a first control signal thereto and application of the free-running clock signals thereto to provide synchronized pulses and is responsive to both a second control signal different from the first control signal thereto and application of the free-running clock signals thereto to cease production of the synchronized pulses at the output terminal. A UART core controls the oscillator and the clock synchronizer and is operated under control of clock signals from the clock synchronizer. The controllable oscillator includes an inverter having a feedback circuit thereacross including a switch responsive to the third control signal to cause the oscillator to cease oscillation. The synchronizer includes a bistable circuit responsive to the first and second control signals and a gate responsive to the bistable circuit and the clock signals for controlling the status of the synchronized pulses at the output terminal.

US Patent:

56195443, Apr 8, 1997

Filed:

Feb 27, 1996

Appl. No.:

8/607840

Inventors:

Clarence D. Lewis - Richardson TX
Mahmoud M. Yazdani - Allen TX
Dinghui Nie - Dallas, TX
Brian T. Deng - Richardson TX
Matthew J. DiMarco - Chicago IL

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 138
H04L 700

US Classification:

375377

Abstract:

A method and apparatus for a circuit physically realizing a Universal Asynchronous Receive/Transmit (UART) circuit 31, 40 having an automatic flow control feature. A preferred embodiment includes a UART 31 provided with additional control circuitry 39, 34 for automatically pausing transfers from the transmit data circuitry 35, 32 in response to a transition at the CTS (Clear to Send) input, and further provided with control circuitry 39 for automatically asserting and deasserting a RTS (Ready to Send) output when a receiver data threshold is reached.

US Patent:

52890600, Feb 22, 1994

Filed:

Sep 16, 1992

Appl. No.:

7/945546

Inventors:

Khodor S. Elnashar - Richardson TX
Jay T. Cantrell - Dallas TX
Clarence D. Lewis - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03B 502

US Classification:

307520

Abstract:

A glitch filter identifies and eliminates positive edge and negative edge glitches without utilizing a high frequency sampling clock. The glitch filter comprises a programmable delay buffer string, two multiple input AND gates and a latch. The buffer string provides a plurality of incrementally delayed signals and utilizes them as signal samples thus simulating a high frequency sampling clock. The two multiple input AND gates serve to eliminate positive or negative edge glitches. The latch outputs the accurate filtered data without any positive or negative edge glitches.

US Patent:

54523249, Sep 19, 1995

Filed:

Sep 23, 1992

Appl. No.:

7/949597

Inventors:

Clarence Lewis - Richardson TX
Khodor Elnashar - Richardson TX
Jay T. Cantrell - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04L 700
H04L 2536

US Classification:

375373

Abstract:

An improved data sampling system for sampling data transmission in a computer system includes a reference clock, a delay locked loop circuit, a packet enable circuit, a delayed selector control circuit, a sample selector, and a sample circuit. The devices may be constructed on a single semiconductor substrate and may be connected to a bus structure having a microcomputer and a plurality of boards coupled to it. The delay locked loop circuit generates accurate delayed clock signals based on the reference clock. A positive edge synchronizer circuit, within the delay locked loop, serves as a programmable phase adjust for the sampling system. The positive edge synchronizer ensures proper phase relationship between the chosen delayed clock signal and the incoming data across semiconductor process variations. Packet enable circuit informs the delayed control circuit and the sample circuit when a start bit or stop bit is initiated in a data packet and enables those circuit blocks accordingly. The delayed selector control circuit uses the delayed clock signals to detect a start bit on a data signal.

Address:

1223 E Overton Rd, Dallas, TX 75216

VIN:

2G1WB58K179171954

Make:

CHEVROLET

Model:

IMPALA

Year:

2007