Connie C Wang

US Patent:

6509267, Jan 21, 2003

Filed:

Jun 20, 2001

Appl. No.:

09/884058

Inventors:

Christy Mei-Chu Woo - Cupertino CA
Suzette K. Pangrle - Cupertino CA
Connie Pin-Chin Wang - Menlo Park CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438687, 438639, 438643, 438678

Abstract:

A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate. The second metal layer serves as a nucleation step for electrolessly plating a copper seed layer.

US Patent:

6927162, Aug 9, 2005

Filed:

Feb 23, 2004

Appl. No.:

10/782874

Inventors:

Wen Yu - Fremont CA, US
Jinsong Yin - Sunnyvale CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Paul Besser - Sunnyvale CA, US
Keizaburo Yoshie - Cupertino CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/4763
H01L021/44

US Classification:

438637, 438644, 438648, 438649, 438675

Abstract:

A method of forming a contact in a semiconductor device deposits a refractory metal contact layer in a contact hole on a conductive region portion in a silicon substrate. The refractory metal contact layer is reacted with the silicide region prior to a plasma treatment of a contact barrier metal layer formed within the contact hole. This prevents portions of the refractory metal contact layer from being nitridated prior to conversion to silicide.

US Patent:

6943096, Sep 13, 2005

Filed:

Sep 17, 2003

Appl. No.:

10/665938

Inventors:

Connie Pin-Chin Wang - Menlo Park CA, US
Suzette K. Pangrle - Cupertino CA, US
Sergey Lopatin - Santa Clara CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/20
H01L021/36

US Classification:

438484, 438761

Abstract:

A semiconductor component having a metallization system that includes a multi-metal seed layer and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a lower level interconnect. A hardmask is formed over the dielectric layer and an opening is etched through the hardmask into the dielectric layer. The opening is lined with a thin conformal barrier material. A plurality of metal oxide layers are formed over the conformal barrier material. The plurality of metal oxide layers are reduced by heat treatment to form a multi-metal seed layer. An electrically conductive material is formed over the multi-metal seed layer.

US Patent:

6952052, Oct 4, 2005

Filed:

Mar 30, 2004

Appl. No.:

10/811860

Inventors:

Amit P. Marathe - Milpitas CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Christy Mei-Chu Woo - Cupertino CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L023/48

US Classification:

257758, 257750, 257751, 257753, 257760, 257762

Abstract:

A composite α-Ta/ graded tantalum nitride /TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous α-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of α-Ta, e. g. , as at a thickness of bout 50 Å to about 100 Å. Embodiments include composite barrier layers having a thickness ratio of α-Ta and graded tantalum nitride: initial TaN of about 2. 5:1 to about 3.

US Patent:

6979625, Dec 27, 2005

Filed:

Nov 12, 2003

Appl. No.:

10/704595

Inventors:

Christy Mei-Chu Woo - Cupertino CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Darrell M. Erb - Los Altos CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/331

US Classification:

438309, 438694, 438361, 438687

Abstract:

High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the relatively wider openings. The filled openings are recessed and a metal capping layer deposited followed by CMP. The metal capping layer prevents diffusion along the copper-capping layer interface while the copper alloy filling the relatively wider openings impedes electromigration along the grain boundaries.

US Patent:

6979642, Dec 27, 2005

Filed:

Jul 28, 2003

Appl. No.:

10/628733

Inventors:

Matthew S. Buynoski - Palo Alto CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Paul R. Besser - Sunnyvale CA, US
Minh Q. Tran - Milpitas CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/283

US Classification:

438660, 438674, 438675, 438685, 438687

Abstract:

A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.

US Patent:

7033940, Apr 25, 2006

Filed:

Mar 30, 2004

Appl. No.:

10/811866

Inventors:

Amit Marathe - Milpitas CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Christy Mei-Chu Woo - Cupertino CA, US
Paul L. King - Mountain View CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/44

US Classification:

438687, 438627, 438637, 438643

Abstract:

A composite α-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an α-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 Å to about 50 Å. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the Nflow rate and/or ratio of the thickness of the combined α-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.

US Patent:

7217660, May 15, 2007

Filed:

Apr 19, 2005

Appl. No.:

11/109964

Inventors:

Connie Pin-Chin Wang - Mountain View CA, US
Paul R. Besser - Sunnyvale CA, US
Jinsong Yin - Sunnyvale CA, US
Hieu T. Pham - Milpitas CA, US
Minh Van Ngo - Fremont CA, US

Assignee:

Spansion LLC - Sunnyvale CA
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/22

US Classification:

438685, 438700

Abstract:

A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.