Cory E Weber

US Patent:

6410359, Jun 25, 2002

Filed:

Mar 26, 2001

Appl. No.:

09/817639

Inventors:

Kevin M. Connolly - Chandler AZ
Jung S. Kang - Chandler AZ
Berni W. Landau - Beaverton OR
James E. Breisch - Chandler AZ
Akira Kakizawa - Phoenix AZ
Mark A. Beiley - Chandler AZ
Cory E. Weber - Beaverton OR
Shaofeng Yu - Lake Oswego OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2100

US Classification:

438 48

Abstract:

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

US Patent:

6800887, Oct 5, 2004

Filed:

Mar 31, 2003

Appl. No.:

10/405110

Inventors:

Cory E. Weber - Hillsboro OR
Mark Armstrong - Portland OR
Harold Kennel - Beaverton OR
Tahir Ghani - Portland OR
Paul A. Packan - Beaverton OR
Scott Thompson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2980

US Classification:

257285, 257287

Abstract:

Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

US Patent:

6838329, Jan 4, 2005

Filed:

Mar 31, 2003

Appl. No.:

10/404878

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark A. Armstrong - Portland OR, US
Stephen M. Cea - Hillsboro OR, US
Giuseppe Curello - Portland OR, US
Aaron D. Lilak - Hillsboro OR, US
Max Wei - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21336
H01L 218238

US Classification:

438217, 438282, 438289, 438524, 438527

Abstract:

A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3.

US Patent:

7129533, Oct 31, 2006

Filed:

Dec 31, 2003

Appl. No.:

10/750498

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark A. Armstrong - Portland OR, US
Stephen M. Cea - Hillsboro OR, US
Giuseppe Curello - Portland OR, US
Aaron D. Lilak - Hillsboro OR, US
Max Wei - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/80

US Classification:

257285, 438162, 438217, 257220

Abstract:

A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3.

US Patent:

7187057, Mar 6, 2007

Filed:

Aug 13, 2004

Appl. No.:

10/918802

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark Armstrong - Portland OR, US
Harold Kennel - Beaverton OR, US
Tahir Ghani - Portland OR, US
Paul A. Packan - Beaverton OR, US
Scott Thompson - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 31/0312

US Classification:

257610, 257617, 257611, 257612, 257607, 257 65, 257E21334

Abstract:

Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

US Patent:

7226824, Jun 5, 2007

Filed:

Aug 13, 2004

Appl. No.:

10/918818

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark Armstrong - Portland OR, US
Harold Kennel - Beaverton OR, US
Tahir Ghani - Portland OR, US
Paul A. Packan - Beaverton OR, US
Scott Thompson - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/338

US Classification:

438174, 438181, 438194, 438197

Abstract:

Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

US Patent:

7226843, Jun 5, 2007

Filed:

Sep 30, 2002

Appl. No.:

10/261715

Inventors:

Cory E. Weber - Hillsboro OR, US
Gerhard Schrom - Hillsboro OR, US
Ian R. Post - Portland OR, US
Mark A. Stettler - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/336
H01L 31/119

US Classification:

438305, 438306, 257344, 257408

Abstract:

A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.

US Patent:

7566605, Jul 28, 2009

Filed:

Mar 31, 2006

Appl. No.:

11/395939

Inventors:

Lucian Shifren - Hillsboro OR, US
Jack T. Kavalieros - Portland OR, US
Steven M. Cea - Hillsboro OR, US
Cory E. Weber - Hillsboro OR, US
Justin K. Brask - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8238
H01L 21/425

US Classification:

438199, 438197, 438514, 438517, 438524

Abstract:

A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.