Craig W Walters

US Patent:

6462665, Oct 8, 2002

Filed:

May 16, 2000

Appl. No.:

09/571447

Inventors:

Peter B. Tarlton - Oceanport NJ
Daniel P. Millerick - Old Bridge NJ
Craig R. Walters - Poughkeepsie NY

Assignee:

Wheelock, Inc. - Long Branch NJ

International Classification:

G01W 100

US Classification:

340601, 340539, 340690, 340 748, 340 75, 7317016, 73384, 4551861, 702 3

Abstract:

A method and apparatus of an alert system for notifying subscribers of weather or hazardous conditions. A weather-tracking source or service broadcasts weather or hazardous conditions across the nation to alert the general public of potentially dangerous climatic and hazardous conditions that may arise from time to time. A weather service provider receives the weather condition broadcasts from the weather-tracking source or service and transmits weather or hazardous condition signals to subscribers having an alert unit. The alert unit is a passive device capable of receiving and warning the subscribers of the weather or hazardous condition broadcasts.

US Patent:

6914695, Jul 5, 2005

Filed:

Aug 8, 2001

Appl. No.:

09/924637

Inventors:

Craig R. Walters - Poughkeepsie NY, US
Scott M. Blackledge - Wappingers Falls NY, US
Steven R. Carlough - Wappingers Falls NY, US
Nathan J. Lee - New City NY, US
Amy S. Purdy - Poughkeepsie NY, US
Adrian O. Robinson - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06K015/00

US Classification:

358 115, 358 11

Abstract:

A digital camera supplies images to a first computer of a network via a receiver which is enabled as a bridge for Bluetooth, wireless LAN and infrared transmission from a digital camera. Once a digital camera is registered in a computer system, transmissions from the camera can be transmitted to the receiving first computer and thereafter transferred over the network for creation of a multi-media file which can be viewed at a private network or Internet accessible second computer.

US Patent:

7383336, Jun 3, 2008

Filed:

Apr 24, 2003

Appl. No.:

10/422864

Inventors:

Gary E. Strait - Poughkeepsie NY, US
Gary A. Van Huben - Poughkeepsie NY, US
Craig R. Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/173
G06F 9/46

US Classification:

709226, 718103, 718104, 719312, 719319, 719328, 719330, 711146, 711147, 711148, 710 28

Abstract:

A method for processing data in a computer system using two main concepts for addressing this situation, from which numerous other implementations is achieved using a first and second main concept. The first is a method of managing a common data path among a plethora of facilities with a decentralized distributed management scheme. The second concept is a method for managing a shared data buffer or group of buffers between multitudes of facilities. By employing the concepts discussed in this invention, one can contemplate a complex dataflow consisting of a multiplicity of resources and data paths, whereby virtually any combination of sharing is possible. A single data path can be shared among multiple sources or sinks. A single resource can be shared, but may have many separate data paths, or all elements of the present invention can be combined to comprise a dataflow with shared resources and shared data paths, both of which are actively managed by completely independent controllers on a separate chip or on the same chip, but with a segregated dataflow.

US Patent:

7523267, Apr 21, 2009

Filed:

Sep 15, 2006

Appl. No.:

11/532156

Inventors:

Craig R. Walters - Highland NY, US
Vesselina K. Papazova - Highland NY, US
Michael A. Blake - Wappingers Falls NY, US
Pak-kin Mak - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

711144, 711145, 711147, 711130

Abstract:

A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.

US Patent:

7685345, Mar 23, 2010

Filed:

Jun 27, 2007

Appl. No.:

11/768934

Inventors:

Deanna Postles Dunn - Poughkeepsie NY, US
Christine Comins Jones - Poughkeepsie NY, US
Arthur J O'Neill - Wappingers Falls NY, US
Vesselina Kirilova Papazova - Highland NY, US
Craig Raymond Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/14
G06F 13/368

US Classification:

710244, 710119, 710120

Abstract:

A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.

US Patent:

7779189, Aug 17, 2010

Filed:

Feb 21, 2008

Appl. No.:

12/035249

Inventors:

Deanna P. Dunn - Hyde Park NY, US
Garrett M. Drapala - Poughkeepsie NY, US
Michael F. Fee - Cold Spring NY, US
Pak-kin Mak - Poughkeepsie NY, US
Craig R. Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/36
G06F 12/00
G06F 13/00
H03M 13/00

US Classification:

710113, 710240, 710309, 711147, 714754

Abstract:

A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.

US Patent:

8131937, Mar 6, 2012

Filed:

Jun 22, 2007

Appl. No.:

11/766977

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Harmony L. Helterhoff - Austin TX, US
Arthur J. O'Neill - Wappingers Falls NY, US
Vesselina K. Papazova - Highland NY, US
Craig R. Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

711133, 711E12055

Abstract:

Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.

US Patent:

8364904, Jan 29, 2013

Filed:

Jun 21, 2010

Appl. No.:

12/819348

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Lawrence D. Curley - Endwell NY, US
Garrett M. Drapala - Poughkeepsie NY, US
Edward J. Kaminski - Wynnewood PA, US
Craig R. Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141

Abstract:

Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.