Cristinel L Zonte

US Patent:

7852144, Dec 14, 2010

Filed:

Sep 28, 2007

Appl. No.:

11/904642

Inventors:

Cristinel Zonte - Colorado Springs CO, US
Vijay Kumar Srinivasa Raghavan - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G05F 3/02

US Classification:

327543, 327513

Abstract:

A relatively precise and accurate current reference system and method are described. The present current reference system and method facilitate realization of relatively high accuracy and precision in current references independent of process, voltage and temperature (PVT) variations. In one embodiment, a current reference system includes an opamp (operational amplifier), a first transistor and second transistor, a first resistor and a second resistor of different temperature coefficients, and a third transistor and fourth transistor. The opamp indicates and corrects the potential difference between a first branch and a second branch. The first transistor and second transistor mirror currents in the first branch and the second branch. The first resistor and a second resistor of different temperature coefficients cause voltage drops across them in a manner that compensates for PTAT variations. The third transistor and fourth transistor provide voltages between respective bases and emitters.

US Patent:

7969804, Jun 28, 2011

Filed:

Dec 24, 2008

Appl. No.:

12/343617

Inventors:

Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Srinivasaraghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 7/00

US Classification:

365206, 365207, 365208, 36518906, 365210

Abstract:

A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to provide accurate sensing, a reference current generator is provided and coupled to the sense amplifier. The reference current generator provides a first reference current having adjustable magnitude and adjustable slope, and a second reference current having adjustable magnitude, but constant slope. The first reference current is supplied to the sense amplifier for sensing the data bit. The second reference current is supplied to a control block for generating clock signals used to control sense amplifier timing.

US Patent:

8125835, Feb 28, 2012

Filed:

Dec 24, 2008

Appl. No.:

12/343658

Inventors:

Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Raghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan I. Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 16/06
G11C 5/14

US Classification:

36518529, 36518518, 365126

Abstract:

In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

US Patent:

8217713, Jul 10, 2012

Filed:

Oct 22, 2007

Appl. No.:

11/975967

Inventors:

Vijay Kumar Srinivasa Raghavan - Colorado Springs CO, US
Cristinel Zonte - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G05F 1/10

US Classification:

327539, 327538, 327541, 323313, 323315

Abstract:

A device for providing a high precision current reference comprising a PTAT generator circuit for supplying a voltage, a high precision current reference offset generator circuit for generating a high precision current offset to compensate for variation in a resistance component due to variation in temperature, and a current adding circuit for aggregating the current from the PTAT generator circuit and the current from the high precision current reference offset generator circuit. In one embodiment, a high precision current reference generated is substantially independent of temperature. On-chip resistors may be used to design a high precision current reference. Accordingly, high precision current reference generated maintains high precision with zero temperature co-efficient using on-chip resistors that are substantially cheaper than off-chip resistors.

US Patent:

8531235, Sep 10, 2013

Filed:

Dec 15, 2011

Appl. No.:

13/326773

Inventors:

Cristinel Zonte - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H01L 35/00

US Classification:

327512, 327539

Abstract:

A current reference circuit configured to generate a reference current with a programmable temperature slope is disclosed. The current reference circuit includes a resistor. The current reference circuit includes a bandgap voltage circuit configured to generate a bandgap voltage and coupled to the resistor. The current reference circuit includes a bias voltage circuit configured to generate a variable-polarity bias voltage and coupled to the bandgap voltage circuit. The bandgap voltage circuit is configured to add the variable-polarity bias voltage to the bandgap voltage to generate the reference current through the resistor.

US Patent:

8542541, Sep 24, 2013

Filed:

Feb 28, 2012

Appl. No.:

13/407660

Inventors:

Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Srinivasaraghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 16/04

US Classification:

36518529, 36518518

Abstract:

In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

US Patent:

8570809, Oct 29, 2013

Filed:

Dec 29, 2011

Appl. No.:

13/340091

Inventors:

Ryan T. Hirose - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Ashish Amonkar - Colorado Springs CO, US
Sean Mulholland - Colorado Springs CO, US
Vijay Raghavan - Colorado Springs CO, US
Cristinel Zonte - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G11C 16/04

US Classification:

36518518, 36518529, 36518909

Abstract:

Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.

US Patent:

7808842, Oct 5, 2010

Filed:

Sep 9, 2008

Appl. No.:

12/207104

Inventors:

Vijay Kumar Srinivasa Raghavan - Colorado Springs CO, US
Cristinel Zonte - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 16/04

US Classification:

36518907, 36518909, 365207, 365205

Abstract:

System and methods to adjust a reference current are disclosed. A current reference circuit generates an adjustable reference current. A microprocessor-based feedback circuit adjusts the reference current, wherein the adjustment is based on read and write parameters attributed to a memory cell.