Curtis R Alexander

US Patent:

6510529, Jan 21, 2003

Filed:

Sep 15, 1999

Appl. No.:

09/397844

Inventors:

Curtis R. Alexander - San Diego CA
Alonso Perez - San Ysidro CA
Thang Doan - Sparks NV

Assignee:

I-Bus - San Diego CA

International Classification:

H02H 305

US Classification:

714 11, 714 55, 714 13

Abstract:

A computer system employs a first computer; a first bus switch coupled to the first computer; a data bus coupled to the first computer via the first bus switch; a second computer; a second bus switch coupled to the second computer, the data bus being coupled to the second computer through the second bus switch; and a monitor system coupled to the first computer, to the first bus switch, and to the second bus switch. The monitor system employs a watchdog timer coupled to a switch over circuit, wherein a watchdog timeout period exceeds a period between executions of a reset code, the reset code being included in software executing on the first computer, wherein a reset signal is generated in response to execution of the reset code, thereby resetting the watchdog timer prior to the watchdog timeout period, and wherein upon a failure in the first computer the reset code is not executed, and therefore the reset signal is not generated, thereby not resetting the watchdog timer prior to the watchdog timeout period, wherein the watchdog timer generates a switch over signal in the event the watchdog timeout period is reached before the watchdog timer is reset, wherein the switch over circuit opens the first data bus switch and closes the second data bus switch in response to the switch over signal.

US Patent:

6708286, Mar 16, 2004

Filed:

Sep 4, 2002

Appl. No.:

10/235513

Inventors:

Curtis R. Alexander - San Diego CA
Alonso Perez - San Ysidro CA
Thang Doan - Sparks NV

Assignee:

I-Bue Corporation - San Jose CA

International Classification:

G06F 1100

US Classification:

714 11, 714 10, 714 12, 714 13, 714 47, 714 22, 714 55

Abstract:

A computer system comprising a first computer coupled to a primary PCI bus via a first PCI bus switch and a second computer coupled to the primary PCI bus via a second PCI bus switch. A monitor system is coupled to both the first and second computers as well as the first and second PCI bus switches. In the event of a malfunction in the first computer, the monitor system decouples the first computer from the primary PCI bus, by opening the first PCI bus switch and coupling the second computer to the primary PCI bus by closing the second PCI bus switch.

US Patent:

49087843, Mar 13, 1990

Filed:

Aug 4, 1987

Appl. No.:

7/081368

Inventors:

Gary W. Box - Golden Valley MN
Thomas S. Foote-Lennox - Bloomington MN
Rodney G. Herreid - St. Louis Park MN
James F. Hoff - Shoreview MN
Dennis J. Leisz - Minnetonka MN
John A. Perlick - Brooklyn Park MN
Terry T. Steeden - Richfield MN
John J. Turner - New Brighton MN
Curtis R. Alexander - Forest Lake MN

Assignee:

Wave Technologies, Inc. - Plymouth MN

International Classification:

G04F 800
G06F 1520

US Classification:

364569

Abstract:

The present invention relates to time measurement apparatus and method for measuring, with picosecond precision, intervals between single edged events, where each measured interval comprises the summation of a rough clock count and fine or calibrated vernier counts of measured fractional clock periods before and after each START and STOP event selected from a calibrated vernier memory. The calibrated vernier memory takes the form of a table of linear voltage versus time developed using pseudo-random generated measurement events of random duration and random separation.